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868d5c6340
The SoC sound core will generate a driver name by normalizing the card name. However, most of the time that name does not tell anything about the driver and is therefore useless for this purpose. Make the driver name more useful by setting it explicitly during card initialization. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210330180657.1867971-1-thierry.reding@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
254 lines
6.8 KiB
C
254 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// tegra_audio_graph_card.c - Audio Graph based Tegra Machine Driver
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//
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// Copyright (c) 2020-2021 NVIDIA CORPORATION. All rights reserved.
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <sound/graph_card.h>
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#include <sound/pcm_params.h>
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#define MAX_PLLA_OUT0_DIV 128
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#define simple_to_tegra_priv(simple) \
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container_of(simple, struct tegra_audio_priv, simple)
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enum srate_type {
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/*
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* Sample rates multiple of 8000 Hz and below are supported:
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* ( 8000, 16000, 32000, 48000, 96000, 192000 Hz )
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*/
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x8_RATE,
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/*
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* Sample rates multiple of 11025 Hz and below are supported:
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* ( 11025, 22050, 44100, 88200, 176400 Hz )
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*/
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x11_RATE,
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NUM_RATE_TYPE,
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};
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struct tegra_audio_priv {
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struct asoc_simple_priv simple;
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struct clk *clk_plla_out0;
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struct clk *clk_plla;
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};
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/* Tegra audio chip data */
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struct tegra_audio_cdata {
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unsigned int plla_rates[NUM_RATE_TYPE];
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unsigned int plla_out0_rates[NUM_RATE_TYPE];
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};
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/* Setup PLL clock as per the given sample rate */
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static int tegra_audio_graph_update_pll(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct asoc_simple_priv *simple = snd_soc_card_get_drvdata(rtd->card);
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struct tegra_audio_priv *priv = simple_to_tegra_priv(simple);
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struct device *dev = rtd->card->dev;
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const struct tegra_audio_cdata *data = of_device_get_match_data(dev);
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unsigned int plla_rate, plla_out0_rate, bclk;
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unsigned int srate = params_rate(params);
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int err;
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switch (srate) {
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case 11025:
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case 22050:
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case 44100:
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case 88200:
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case 176400:
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plla_out0_rate = data->plla_out0_rates[x11_RATE];
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plla_rate = data->plla_rates[x11_RATE];
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break;
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case 8000:
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case 16000:
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case 32000:
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case 48000:
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case 96000:
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case 192000:
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plla_out0_rate = data->plla_out0_rates[x8_RATE];
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plla_rate = data->plla_rates[x8_RATE];
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break;
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default:
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dev_err(rtd->card->dev, "Unsupported sample rate %u\n",
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srate);
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return -EINVAL;
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}
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/*
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* Below is the clock relation:
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*
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* PLLA
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* |
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* |--> PLLA_OUT0
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* |
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* |---> I2S modules
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* |
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* |---> DMIC modules
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* |
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* |---> DSPK modules
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*
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*
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* Default PLLA_OUT0 rate might be too high when I/O is running
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* at minimum PCM configurations. This may result in incorrect
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* clock rates and glitchy audio. The maximum divider is 128
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* and any thing higher than that won't work. Thus reduce PLLA_OUT0
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* to work for lower configurations.
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*
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* This problem is seen for I2S only, as DMIC and DSPK minimum
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* clock requirements are under allowed divider limits.
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*/
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bclk = srate * params_channels(params) * params_width(params);
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if (div_u64(plla_out0_rate, bclk) > MAX_PLLA_OUT0_DIV)
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plla_out0_rate >>= 1;
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dev_dbg(rtd->card->dev,
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"Update clock rates: PLLA(= %u Hz) and PLLA_OUT0(= %u Hz)\n",
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plla_rate, plla_out0_rate);
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/* Set PLLA rate */
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err = clk_set_rate(priv->clk_plla, plla_rate);
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if (err) {
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dev_err(rtd->card->dev,
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"Can't set plla rate for %u, err: %d\n",
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plla_rate, err);
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return err;
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}
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/* Set PLLA_OUT0 rate */
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err = clk_set_rate(priv->clk_plla_out0, plla_out0_rate);
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if (err) {
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dev_err(rtd->card->dev,
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"Can't set plla_out0 rate %u, err: %d\n",
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plla_out0_rate, err);
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return err;
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}
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return err;
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}
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static int tegra_audio_graph_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
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int err;
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/*
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* This gets called for each DAI link (FE or BE) when DPCM is used.
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* We may not want to update PLLA rate for each call. So PLLA update
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* must be restricted to external I/O links (I2S, DMIC or DSPK) since
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* they actually depend on it. I/O modules update their clocks in
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* hw_param() of their respective component driver and PLLA rate
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* update here helps them to derive appropriate rates.
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*
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* TODO: When more HW accelerators get added (like sample rate
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* converter, volume gain controller etc., which don't really
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* depend on PLLA) we need a better way to filter here.
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*/
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if (cpu_dai->driver->ops && rtd->dai_link->no_pcm) {
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err = tegra_audio_graph_update_pll(substream, params);
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if (err)
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return err;
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}
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return asoc_simple_hw_params(substream, params);
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}
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static const struct snd_soc_ops tegra_audio_graph_ops = {
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.startup = asoc_simple_startup,
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.shutdown = asoc_simple_shutdown,
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.hw_params = tegra_audio_graph_hw_params,
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};
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static int tegra_audio_graph_card_probe(struct snd_soc_card *card)
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{
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struct asoc_simple_priv *simple = snd_soc_card_get_drvdata(card);
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struct tegra_audio_priv *priv = simple_to_tegra_priv(simple);
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priv->clk_plla = devm_clk_get(card->dev, "pll_a");
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if (IS_ERR(priv->clk_plla)) {
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dev_err(card->dev, "Can't retrieve clk pll_a\n");
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return PTR_ERR(priv->clk_plla);
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}
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priv->clk_plla_out0 = devm_clk_get(card->dev, "plla_out0");
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if (IS_ERR(priv->clk_plla_out0)) {
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dev_err(card->dev, "Can't retrieve clk plla_out0\n");
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return PTR_ERR(priv->clk_plla_out0);
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}
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return audio_graph_card_probe(card);
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}
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static int tegra_audio_graph_probe(struct platform_device *pdev)
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{
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struct tegra_audio_priv *priv;
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struct device *dev = &pdev->dev;
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struct snd_soc_card *card;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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card = simple_priv_to_card(&priv->simple);
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card->driver_name = "tegra-ape";
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card->probe = tegra_audio_graph_card_probe;
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/* audio_graph_parse_of() depends on below */
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card->component_chaining = 1;
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priv->simple.ops = &tegra_audio_graph_ops;
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priv->simple.force_dpcm = 1;
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return audio_graph_parse_of(&priv->simple, dev);
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}
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static const struct tegra_audio_cdata tegra210_data = {
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/* PLLA */
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.plla_rates[x8_RATE] = 368640000,
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.plla_rates[x11_RATE] = 338688000,
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/* PLLA_OUT0 */
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.plla_out0_rates[x8_RATE] = 49152000,
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.plla_out0_rates[x11_RATE] = 45158400,
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};
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static const struct tegra_audio_cdata tegra186_data = {
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/* PLLA */
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.plla_rates[x8_RATE] = 245760000,
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.plla_rates[x11_RATE] = 270950400,
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/* PLLA_OUT0 */
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.plla_out0_rates[x8_RATE] = 49152000,
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.plla_out0_rates[x11_RATE] = 45158400,
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};
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static const struct of_device_id graph_of_tegra_match[] = {
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{ .compatible = "nvidia,tegra210-audio-graph-card",
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.data = &tegra210_data },
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{ .compatible = "nvidia,tegra186-audio-graph-card",
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.data = &tegra186_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, graph_of_tegra_match);
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static struct platform_driver tegra_audio_graph_card = {
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.driver = {
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.name = "tegra-audio-graph-card",
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.pm = &snd_soc_pm_ops,
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.of_match_table = graph_of_tegra_match,
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},
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.probe = tegra_audio_graph_probe,
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.remove = audio_graph_remove,
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};
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module_platform_driver(tegra_audio_graph_card);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("ASoC Tegra Audio Graph Sound Card");
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MODULE_AUTHOR("Sameer Pujar <spujar@nvidia.com>");
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