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678d536bb4
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 8341dc04df
("iio:dac: Add support for the ad5449")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-47-jic23@kernel.org
368 lines
8.3 KiB
C
368 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AD5415, AD5426, AD5429, AD5432, AD5439, AD5443, AD5449 Digital to Analog
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* Converter driver.
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*
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* Copyright 2012 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/regulator/consumer.h>
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#include <asm/unaligned.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/platform_data/ad5449.h>
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#define AD5449_MAX_CHANNELS 2
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#define AD5449_MAX_VREFS 2
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#define AD5449_CMD_NOOP 0x0
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#define AD5449_CMD_LOAD_AND_UPDATE(x) (0x1 + (x) * 3)
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#define AD5449_CMD_READ(x) (0x2 + (x) * 3)
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#define AD5449_CMD_LOAD(x) (0x3 + (x) * 3)
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#define AD5449_CMD_CTRL 13
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#define AD5449_CTRL_SDO_OFFSET 10
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#define AD5449_CTRL_DAISY_CHAIN BIT(9)
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#define AD5449_CTRL_HCLR_TO_MIDSCALE BIT(8)
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#define AD5449_CTRL_SAMPLE_RISING BIT(7)
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/**
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* struct ad5449_chip_info - chip specific information
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* @channels: Channel specification
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* @num_channels: Number of channels
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* @has_ctrl: Chip has a control register
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*/
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struct ad5449_chip_info {
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const struct iio_chan_spec *channels;
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unsigned int num_channels;
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bool has_ctrl;
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};
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/**
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* struct ad5449 - driver instance specific data
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* @spi: the SPI device for this driver instance
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* @chip_info: chip model specific constants, available modes etc
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* @vref_reg: vref supply regulators
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* @has_sdo: whether the SDO line is connected
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* @dac_cache: Cache for the DAC values
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* @data: spi transfer buffers
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* @lock: lock to protect the data buffer during SPI ops
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*/
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struct ad5449 {
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struct spi_device *spi;
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const struct ad5449_chip_info *chip_info;
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struct regulator_bulk_data vref_reg[AD5449_MAX_VREFS];
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struct mutex lock;
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bool has_sdo;
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uint16_t dac_cache[AD5449_MAX_CHANNELS];
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/*
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* DMA (thus cache coherency maintenance) may require the
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* transfer buffers to live in their own cache lines.
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*/
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__be16 data[2] __aligned(IIO_DMA_MINALIGN);
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};
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enum ad5449_type {
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ID_AD5426,
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ID_AD5429,
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ID_AD5432,
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ID_AD5439,
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ID_AD5443,
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ID_AD5449,
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};
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static int ad5449_write(struct iio_dev *indio_dev, unsigned int addr,
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unsigned int val)
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{
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struct ad5449 *st = iio_priv(indio_dev);
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int ret;
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mutex_lock(&st->lock);
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st->data[0] = cpu_to_be16((addr << 12) | val);
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ret = spi_write(st->spi, st->data, 2);
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mutex_unlock(&st->lock);
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return ret;
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}
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static int ad5449_read(struct iio_dev *indio_dev, unsigned int addr,
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unsigned int *val)
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{
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struct ad5449 *st = iio_priv(indio_dev);
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int ret;
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struct spi_transfer t[] = {
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{
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.tx_buf = &st->data[0],
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.len = 2,
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.cs_change = 1,
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}, {
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.tx_buf = &st->data[1],
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.rx_buf = &st->data[1],
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.len = 2,
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},
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};
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mutex_lock(&st->lock);
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st->data[0] = cpu_to_be16(addr << 12);
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st->data[1] = cpu_to_be16(AD5449_CMD_NOOP);
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ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
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if (ret < 0)
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goto out_unlock;
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*val = be16_to_cpu(st->data[1]);
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out_unlock:
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mutex_unlock(&st->lock);
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return ret;
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}
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static int ad5449_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val, int *val2, long info)
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{
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struct ad5449 *st = iio_priv(indio_dev);
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struct regulator_bulk_data *reg;
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int scale_uv;
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int ret;
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switch (info) {
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case IIO_CHAN_INFO_RAW:
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if (st->has_sdo) {
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ret = ad5449_read(indio_dev,
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AD5449_CMD_READ(chan->address), val);
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if (ret)
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return ret;
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*val &= 0xfff;
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} else {
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*val = st->dac_cache[chan->address];
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}
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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reg = &st->vref_reg[chan->channel];
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scale_uv = regulator_get_voltage(reg->consumer);
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if (scale_uv < 0)
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return scale_uv;
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*val = scale_uv / 1000;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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break;
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}
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return -EINVAL;
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}
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static int ad5449_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int val, int val2, long info)
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{
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struct ad5449 *st = iio_priv(indio_dev);
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int ret;
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switch (info) {
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case IIO_CHAN_INFO_RAW:
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if (val < 0 || val >= (1 << chan->scan_type.realbits))
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return -EINVAL;
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ret = ad5449_write(indio_dev,
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AD5449_CMD_LOAD_AND_UPDATE(chan->address),
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val << chan->scan_type.shift);
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if (ret == 0)
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st->dac_cache[chan->address] = val;
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static const struct iio_info ad5449_info = {
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.read_raw = ad5449_read_raw,
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.write_raw = ad5449_write_raw,
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};
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#define AD5449_CHANNEL(chan, bits) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.output = 1, \
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.channel = (chan), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.address = (chan), \
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.scan_type = { \
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.sign = 'u', \
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.realbits = (bits), \
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.storagebits = 16, \
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.shift = 12 - (bits), \
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}, \
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}
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#define DECLARE_AD5449_CHANNELS(name, bits) \
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const struct iio_chan_spec name[] = { \
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AD5449_CHANNEL(0, bits), \
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AD5449_CHANNEL(1, bits), \
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}
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static DECLARE_AD5449_CHANNELS(ad5429_channels, 8);
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static DECLARE_AD5449_CHANNELS(ad5439_channels, 10);
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static DECLARE_AD5449_CHANNELS(ad5449_channels, 12);
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static const struct ad5449_chip_info ad5449_chip_info[] = {
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[ID_AD5426] = {
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.channels = ad5429_channels,
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.num_channels = 1,
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.has_ctrl = false,
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},
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[ID_AD5429] = {
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.channels = ad5429_channels,
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.num_channels = 2,
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.has_ctrl = true,
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},
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[ID_AD5432] = {
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.channels = ad5439_channels,
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.num_channels = 1,
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.has_ctrl = false,
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},
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[ID_AD5439] = {
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.channels = ad5439_channels,
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.num_channels = 2,
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.has_ctrl = true,
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},
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[ID_AD5443] = {
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.channels = ad5449_channels,
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.num_channels = 1,
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.has_ctrl = false,
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},
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[ID_AD5449] = {
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.channels = ad5449_channels,
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.num_channels = 2,
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.has_ctrl = true,
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},
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};
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static const char *ad5449_vref_name(struct ad5449 *st, int n)
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{
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if (st->chip_info->num_channels == 1)
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return "VREF";
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if (n == 0)
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return "VREFA";
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else
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return "VREFB";
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}
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static int ad5449_spi_probe(struct spi_device *spi)
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{
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struct ad5449_platform_data *pdata = spi->dev.platform_data;
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const struct spi_device_id *id = spi_get_device_id(spi);
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struct iio_dev *indio_dev;
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struct ad5449 *st;
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unsigned int i;
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int ret;
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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if (indio_dev == NULL)
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return -ENOMEM;
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st = iio_priv(indio_dev);
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spi_set_drvdata(spi, indio_dev);
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st->chip_info = &ad5449_chip_info[id->driver_data];
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st->spi = spi;
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for (i = 0; i < st->chip_info->num_channels; ++i)
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st->vref_reg[i].supply = ad5449_vref_name(st, i);
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ret = devm_regulator_bulk_get(&spi->dev, st->chip_info->num_channels,
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st->vref_reg);
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if (ret)
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return ret;
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ret = regulator_bulk_enable(st->chip_info->num_channels, st->vref_reg);
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if (ret)
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return ret;
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indio_dev->name = id->name;
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indio_dev->info = &ad5449_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = st->chip_info->channels;
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indio_dev->num_channels = st->chip_info->num_channels;
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mutex_init(&st->lock);
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if (st->chip_info->has_ctrl) {
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unsigned int ctrl = 0x00;
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if (pdata) {
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if (pdata->hardware_clear_to_midscale)
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ctrl |= AD5449_CTRL_HCLR_TO_MIDSCALE;
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ctrl |= pdata->sdo_mode << AD5449_CTRL_SDO_OFFSET;
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st->has_sdo = pdata->sdo_mode != AD5449_SDO_DISABLED;
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} else {
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st->has_sdo = true;
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}
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ad5449_write(indio_dev, AD5449_CMD_CTRL, ctrl);
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}
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ret = iio_device_register(indio_dev);
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if (ret)
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goto error_disable_reg;
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return 0;
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error_disable_reg:
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regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
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return ret;
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}
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static void ad5449_spi_remove(struct spi_device *spi)
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{
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struct iio_dev *indio_dev = spi_get_drvdata(spi);
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struct ad5449 *st = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
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}
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static const struct spi_device_id ad5449_spi_ids[] = {
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{ "ad5415", ID_AD5449 },
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{ "ad5426", ID_AD5426 },
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{ "ad5429", ID_AD5429 },
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{ "ad5432", ID_AD5432 },
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{ "ad5439", ID_AD5439 },
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{ "ad5443", ID_AD5443 },
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{ "ad5449", ID_AD5449 },
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{}
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};
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MODULE_DEVICE_TABLE(spi, ad5449_spi_ids);
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static struct spi_driver ad5449_spi_driver = {
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.driver = {
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.name = "ad5449",
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},
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.probe = ad5449_spi_probe,
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.remove = ad5449_spi_remove,
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.id_table = ad5449_spi_ids,
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};
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module_spi_driver(ad5449_spi_driver);
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MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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MODULE_DESCRIPTION("Analog Devices AD5449 and similar DACs");
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MODULE_LICENSE("GPL v2");
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