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6d803ba736
factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
77 lines
1.6 KiB
C
77 lines
1.6 KiB
C
#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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static struct clk master_clk = {
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.flags = CLK_ENABLE_ON_INIT,
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.rate = CONFIG_SH_PCLK_FREQ,
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};
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static struct clk peripheral_clk = {
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk bus_clk = {
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk cpu_clk = {
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.parent = &master_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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/*
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* The ordering of these clocks matters, do not change it.
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*/
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static struct clk *onchip_clocks[] = {
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&master_clk,
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&peripheral_clk,
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&bus_clk,
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&cpu_clk,
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};
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("master_clk", &master_clk),
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CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
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CLKDEV_CON_ID("bus_clk", &bus_clk),
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CLKDEV_CON_ID("cpu_clk", &cpu_clk),
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};
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int __init __deprecated cpg_clk_init(void)
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{
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
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struct clk *clk = onchip_clocks[i];
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arch_init_clk_ops(&clk->ops, i);
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if (clk->ops)
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ret |= clk_register(clk);
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}
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
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clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
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clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
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clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
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return ret;
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}
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/*
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* Placeholder for compatability, until the lazy CPUs do this
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* on their own.
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*/
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int __init __weak arch_clk_init(void)
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{
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return cpg_clk_init();
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}
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