mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-16 08:44:21 +08:00
56a5b7910e
Add SoundWire specific parts and extend common ones already split from I2C. Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com> Signed-off-by: Naveen Manohar <naveen.m@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@linux.intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Link: https://lore.kernel.org/r/20200708203215.231776-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
73 lines
2.9 KiB
C
73 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/* Copyright (c) 2020 Maxim Integrated */
|
|
|
|
#ifndef _MAX98373_SDW_H
|
|
#define _MAX98373_SDW_H
|
|
|
|
#include "max98373.h"
|
|
|
|
/* SoundWire Slave Control Port (SCP) */
|
|
#define MAX98373_R0040_SCP_INIT_STAT_1 0x0040
|
|
#define MAX98373_R0041_SCP_INIT_MASK_1 0x0041
|
|
#define MAX98373_R0042_SCP_INIT_STAT_2 0x0042
|
|
#define MAX98373_R0044_SCP_CTRL 0x0044
|
|
#define MAX98373_R0045_SCP_SYSTEM_CTRL 0x0045
|
|
#define MAX98373_R0046_SCP_DEV_NUMBER 0x0046
|
|
#define MAX98373_R0050_SCP_DEV_ID_0 0x0050
|
|
#define MAX98373_R0051_SCP_DEV_ID_1 0x0051
|
|
#define MAX98373_R0052_SCP_DEV_ID_2 0x0052
|
|
#define MAX98373_R0053_SCP_DEV_ID_3 0x0053
|
|
#define MAX98373_R0054_SCP_DEV_ID_4 0x0054
|
|
#define MAX98373_R0055_SCP_DEV_ID_5 0x0055
|
|
#define MAX98373_R0060_SCP_FRAME_CTLR 0x0060
|
|
#define MAX98373_R0070_SCP_FRAME_CTLR 0x0070
|
|
|
|
/* SoundWire Device Data Port (DP) */
|
|
/* Data Port 1 Registers */
|
|
#define MAX98373_R0100_DP1_INIT_STAT 0x0100
|
|
#define MAX98373_R0101_DP1_INIT_MASK 0x0101
|
|
#define MAX98373_R0102_DP1_PORT_CTRL 0x0102
|
|
#define MAX98373_R0103_DP1_BLOCK_CTRL_1 0x0103
|
|
#define MAX98373_R0104_DP1_PREPARE_STATUS 0x0104
|
|
#define MAX98373_R0105_DP1_PREPARE_CTRL 0x0105
|
|
/* Data Port 1 Bank 0 Registers */
|
|
#define MAX98373_R0120_DP1_CHANNEL_EN 0x0120
|
|
#define MAX98373_R0122_DP1_SAMPLE_CTRL1 0x0122
|
|
#define MAX98373_R0123_DP1_SAMPLE_CTRL2 0x0123
|
|
#define MAX98373_R0124_DP1_OFFSET_CTRL1 0x0124
|
|
#define MAX98373_R0125_DP1_OFFSET_CTRL2 0x0125
|
|
#define MAX98373_R0126_DP1_HCTRL 0x0126
|
|
#define MAX98373_R0127_DP1_BLOCK_CTRL3 0x0127
|
|
/* Data Port 1 Bank 1 Registers */
|
|
#define MAX98373_R0130_DP1_CHANNEL_EN 0x0130
|
|
#define MAX98373_R0132_DP1_SAMPLE_CTRL1 0x0132
|
|
#define MAX98373_R0133_DP1_SAMPLE_CTRL2 0x0133
|
|
#define MAX98373_R0134_DP1_OFFSET_CTRL1 0x0134
|
|
#define MAX98373_R0135_DP1_OFFSET_CTRL2 0x0135
|
|
#define MAX98373_R0136_DP1_HCTRL 0x0136
|
|
#define MAX98373_R0137_DP1_BLOCK_CTRL3 0x0137
|
|
/* Data Port 3 Registers */
|
|
#define MAX98373_R0300_DP3_INIT_STAT 0x0300
|
|
#define MAX98373_R0301_DP3_INIT_MASK 0x0301
|
|
#define MAX98373_R0302_DP3_PORT_CTRL 0x0302
|
|
#define MAX98373_R0303_DP3_BLOCK_CTRL_1 0x0303
|
|
#define MAX98373_R0304_DP3_PREPARE_STATUS 0x0304
|
|
#define MAX98373_R0305_DP3_PREPARE_CTRL 0x0305
|
|
/* Data Port 3 Bank 0 Registers */
|
|
#define MAX98373_R0320_DP3_CHANNEL_EN 0x0320
|
|
#define MAX98373_R0322_DP3_SAMPLE_CTRL1 0x0322
|
|
#define MAX98373_R0323_DP3_SAMPLE_CTRL2 0x0323
|
|
#define MAX98373_R0324_DP3_OFFSET_CTRL1 0x0324
|
|
#define MAX98373_R0325_DP3_OFFSET_CTRL2 0x0325
|
|
#define MAX98373_R0326_DP3_HCTRL 0x0326
|
|
#define MAX98373_R0327_DP3_BLOCK_CTRL3 0x0327
|
|
/* Data Port 3 Bank 1 Registers */
|
|
#define MAX98373_R0330_DP3_CHANNEL_EN 0x0330
|
|
#define MAX98373_R0332_DP3_SAMPLE_CTRL1 0x0332
|
|
#define MAX98373_R0333_DP3_SAMPLE_CTRL2 0x0333
|
|
#define MAX98373_R0334_DP3_OFFSET_CTRL1 0x0334
|
|
#define MAX98373_R0335_DP3_OFFSET_CTRL2 0x0335
|
|
#define MAX98373_R0336_DP3_HCTRL 0x0336
|
|
#define MAX98373_R0337_DP3_BLOCK_CTRL3 0x0337
|
|
#endif
|