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31b1fed36e
There are four clocks that vop module would need to operate:
DCLK_VOP, HCLK_VOP, SCLK_VOP, ACLK_VOP,
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
229 lines
5.3 KiB
C
229 lines
5.3 KiB
C
/*
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* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
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* Author: Jeffy Chen <jeffy.chen@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define ARMCLK 5
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/* sclk gates (special clocks) */
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#define SCLK_SPI0 65
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#define SCLK_NANDC 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_TSADC 72
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_I2S0 80
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#define SCLK_I2S1 81
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#define SCLK_I2S2 82
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#define SCLK_SPDIF 83
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_TIMER4 89
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#define SCLK_TIMER5 90
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#define SCLK_I2S_OUT 113
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#define SCLK_SDMMC_DRV 114
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#define SCLK_SDIO_DRV 115
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_VOP 122
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/* dclk gates */
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#define DCLK_VOP 190
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/* aclk gates */
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#define ACLK_DMAC 194
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#define ACLK_PERI 210
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#define ACLK_VOP 211
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_GRF 329
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_I2C3 335
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#define PCLK_SPI0 338
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_TSADC 344
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_PERI 363
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/* hclk gates */
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#define HCLK_VOP 452
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#define HCLK_NANDC 453
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#define HCLK_SDMMC 456
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#define HCLK_SDIO 457
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#define HCLK_EMMC 459
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#define HCLK_PERI 478
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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/* soft-reset indices */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE2_DBG 10
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#define SRST_CORE3_DBG 11
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#define SRST_TOPDBG 12
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#define SRST_ACLK_CORE 13
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#define SRST_NOC 14
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#define SRST_L2C 15
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#define SRST_CPUSYS_H 18
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#define SRST_BUSSYS_H 19
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#define SRST_SPDIF 20
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#define SRST_INTMEM 21
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#define SRST_ROM 22
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#define SRST_OTG_ADP 23
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#define SRST_I2S0 24
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#define SRST_I2S1 25
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#define SRST_I2S2 26
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#define SRST_ACODEC_P 27
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#define SRST_DFIMON 28
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#define SRST_MSCH 29
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#define SRST_EFUSE1024 30
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#define SRST_EFUSE256 31
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_GPIO3 35
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#define SRST_PERIPH_NOC_A 36
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#define SRST_PERIPH_NOC_BUS_H 37
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#define SRST_PERIPH_NOC_P 38
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#define SRST_UART0 39
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#define SRST_UART1 40
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#define SRST_UART2 41
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#define SRST_PHYNOC 42
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#define SRST_I2C0 43
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#define SRST_I2C1 44
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#define SRST_I2C2 45
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#define SRST_I2C3 46
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#define SRST_PWM 48
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#define SRST_A53_GIC 49
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#define SRST_DAP 51
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#define SRST_DAP_NOC 52
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#define SRST_CRYPTO 53
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#define SRST_SGRF 54
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#define SRST_GRF 55
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#define SRST_GMAC 56
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#define SRST_PERIPH_NOC_H 58
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#define SRST_MACPHY 63
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#define SRST_DMA 64
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#define SRST_NANDC 68
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#define SRST_USBOTG 69
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#define SRST_OTGC 70
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#define SRST_USBHOST0 71
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#define SRST_HOST_CTRL0 72
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#define SRST_USBHOST1 73
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#define SRST_HOST_CTRL1 74
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#define SRST_USBHOST2 75
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#define SRST_HOST_CTRL2 76
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#define SRST_USBPOR0 77
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#define SRST_USBPOR1 78
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#define SRST_DDRMSCH 79
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#define SRST_SMART_CARD 80
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#define SRST_SDMMC 81
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#define SRST_SDIO 82
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#define SRST_EMMC 83
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#define SRST_SPI 84
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#define SRST_TSP_H 85
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#define SRST_TSP 86
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#define SRST_TSADC 87
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#define SRST_DDRPHY 88
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#define SRST_DDRPHY_P 89
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#define SRST_DDRCTRL 90
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#define SRST_DDRCTRL_P 91
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#define SRST_HOST0_ECHI 92
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#define SRST_HOST1_ECHI 93
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#define SRST_HOST2_ECHI 94
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#define SRST_VOP_NOC_A 95
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#define SRST_HDMI_P 96
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#define SRST_VIO_ARBI_H 97
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#define SRST_IEP_NOC_A 98
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#define SRST_VIO_NOC_H 99
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#define SRST_VOP_A 100
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#define SRST_VOP_H 101
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#define SRST_VOP_D 102
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#define SRST_UTMI0 103
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#define SRST_UTMI1 104
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#define SRST_UTMI2 105
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#define SRST_UTMI3 106
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#define SRST_RGA 107
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#define SRST_RGA_NOC_A 108
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#define SRST_RGA_A 109
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#define SRST_RGA_H 110
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#define SRST_HDCP_A 111
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#define SRST_VPU_A 112
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#define SRST_VPU_H 113
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#define SRST_VPU_NOC_A 116
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#define SRST_VPU_NOC_H 117
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#define SRST_RKVDEC_A 118
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#define SRST_RKVDEC_NOC_A 119
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#define SRST_RKVDEC_H 120
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#define SRST_RKVDEC_NOC_H 121
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#define SRST_RKVDEC_CORE 122
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#define SRST_RKVDEC_CABAC 123
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#define SRST_IEP_A 124
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#define SRST_IEP_H 125
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#define SRST_GPU_A 126
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#define SRST_GPU_NOC_A 127
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#define SRST_CORE_DBG 128
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#define SRST_DBG_P 129
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#define SRST_TIMER0 130
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#define SRST_TIMER1 131
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#define SRST_TIMER2 132
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#define SRST_TIMER3 133
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#define SRST_TIMER4 134
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#define SRST_TIMER5 135
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#define SRST_VIO_H2P 136
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#define SRST_HDMIPHY 139
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#define SRST_VDAC 140
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#define SRST_TIMER_6CH_P 141
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#endif
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