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3c938cc5ce
In case of PREEMPT_RT, there is a raw_spinlock -> spinlock dependency as the lockdep report shows. __irq_set_handler irq_get_desc_buslock __irq_get_desc_lock raw_spin_lock_irqsave(&desc->lock, *flags); // raw spinlock get here __irq_do_set_handler mask_ack_irq dwapb_irq_ack spin_lock_irqsave(&gc->bgpio_lock, flags); // sleep able spinlock irq_put_desc_busunlock Replace with a raw lock to avoid BUGs. This lock is only used to access registers, and It's safe to replace with the raw lock without bad influence. [ 15.090359][ T1] ============================= [ 15.090365][ T1] [ BUG: Invalid wait context ] [ 15.090373][ T1] 5.10.59-rt52-00983-g186a6841c682-dirty #3 Not tainted [ 15.090386][ T1] ----------------------------- [ 15.090392][ T1] swapper/0/1 is trying to lock: [ 15.090402][ T1] 70ff00018507c188 (&gc->bgpio_lock){....}-{3:3}, at: _raw_spin_lock_irqsave+0x1c/0x28 [ 15.090470][ T1] other info that might help us debug this: [ 15.090477][ T1] context-{5:5} [ 15.090485][ T1] 3 locks held by swapper/0/1: [ 15.090497][ T1] #0: c2ff0001816de1a0 (&dev->mutex){....}-{4:4}, at: __device_driver_lock+0x98/0x104 [ 15.090553][ T1] #1: ffff90001485b4b8 (irq_domain_mutex){+.+.}-{4:4}, at: irq_domain_associate+0xbc/0x6d4 [ 15.090606][ T1] #2: 4bff000185d7a8e0 (lock_class){....}-{2:2}, at: _raw_spin_lock_irqsave+0x1c/0x28 [ 15.090654][ T1] stack backtrace: [ 15.090661][ T1] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.10.59-rt52-00983-g186a6841c682-dirty #3 [ 15.090682][ T1] Hardware name: Horizon Robotics Journey 5 DVB (DT) [ 15.090692][ T1] Call trace: ...... [ 15.090811][ T1] _raw_spin_lock_irqsave+0x1c/0x28 [ 15.090828][ T1] dwapb_irq_ack+0xb4/0x300 [ 15.090846][ T1] __irq_do_set_handler+0x494/0xb2c [ 15.090864][ T1] __irq_set_handler+0x74/0x114 [ 15.090881][ T1] irq_set_chip_and_handler_name+0x44/0x58 [ 15.090900][ T1] gpiochip_irq_map+0x210/0x644 Signed-off-by: Schspa Shi <schspa@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Doug Berger <opendmb@gmail.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
784 lines
21 KiB
C
784 lines
21 KiB
C
/*
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* Copyright (C) 2015-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/module.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/interrupt.h>
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enum gio_reg_index {
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GIO_REG_ODEN = 0,
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GIO_REG_DATA,
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GIO_REG_IODIR,
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GIO_REG_EC,
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GIO_REG_EI,
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GIO_REG_MASK,
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GIO_REG_LEVEL,
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GIO_REG_STAT,
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NUMBER_OF_GIO_REGISTERS
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};
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#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
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#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
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#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
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#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
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#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
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#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
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#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
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#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
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#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
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#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
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struct brcmstb_gpio_bank {
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struct list_head node;
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int id;
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struct gpio_chip gc;
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struct brcmstb_gpio_priv *parent_priv;
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u32 width;
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u32 wake_active;
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u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
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};
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struct brcmstb_gpio_priv {
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struct list_head bank_list;
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void __iomem *reg_base;
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struct platform_device *pdev;
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struct irq_domain *irq_domain;
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struct irq_chip irq_chip;
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int parent_irq;
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int gpio_base;
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int num_gpios;
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int parent_wake_irq;
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};
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#define MAX_GPIO_PER_BANK 32
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#define GPIO_BANK(gpio) ((gpio) >> 5)
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/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
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#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
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static inline struct brcmstb_gpio_priv *
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brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
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{
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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return bank->parent_priv;
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}
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static unsigned long
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__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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{
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void __iomem *reg_base = bank->parent_priv->reg_base;
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return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
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bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
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}
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static unsigned long
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brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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{
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unsigned long status;
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unsigned long flags;
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raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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status = __brcmstb_gpio_get_active_irqs(bank);
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raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return status;
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}
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static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
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struct brcmstb_gpio_bank *bank)
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{
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return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
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}
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static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
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unsigned int hwirq, bool enable)
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{
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struct gpio_chip *gc = &bank->gc;
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
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u32 imask;
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unsigned long flags;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
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if (enable)
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imask |= mask;
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else
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imask &= ~mask;
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gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
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/* gc_offset is relative to this gpio_chip; want real offset */
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int hwirq = offset + (gc->base - priv->gpio_base);
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if (hwirq >= priv->num_gpios)
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return -ENXIO;
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return irq_create_mapping(priv->irq_domain, hwirq);
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}
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/* -------------------- IRQ chip functions -------------------- */
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static void brcmstb_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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brcmstb_gpio_set_imask(bank, d->hwirq, false);
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}
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static void brcmstb_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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brcmstb_gpio_set_imask(bank, d->hwirq, true);
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}
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static void brcmstb_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
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gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
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}
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static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
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u32 edge_insensitive, iedge_insensitive;
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u32 edge_config, iedge_config;
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u32 level, ilevel;
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unsigned long flags;
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switch (type) {
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case IRQ_TYPE_LEVEL_LOW:
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level = mask;
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edge_config = 0;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level = mask;
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edge_config = mask;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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level = 0;
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edge_config = 0;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_EDGE_RISING:
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level = 0;
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edge_config = mask;
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edge_insensitive = 0;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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level = 0;
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edge_config = 0; /* don't care, but want known value */
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edge_insensitive = mask;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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iedge_config = bank->gc.read_reg(priv->reg_base +
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GIO_EC(bank->id)) & ~mask;
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iedge_insensitive = bank->gc.read_reg(priv->reg_base +
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GIO_EI(bank->id)) & ~mask;
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ilevel = bank->gc.read_reg(priv->reg_base +
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GIO_LEVEL(bank->id)) & ~mask;
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bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
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iedge_config | edge_config);
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bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
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iedge_insensitive | edge_insensitive);
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bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
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ilevel | level);
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raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return 0;
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}
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static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
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unsigned int enable)
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{
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int ret = 0;
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if (enable)
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ret = enable_irq_wake(priv->parent_wake_irq);
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else
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ret = disable_irq_wake(priv->parent_wake_irq);
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if (ret)
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dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
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enable ? "enable" : "disable");
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return ret;
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}
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static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
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/*
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* Do not do anything specific for now, suspend/resume callbacks will
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* configure the interrupt mask appropriately
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*/
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if (enable)
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bank->wake_active |= mask;
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else
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bank->wake_active &= ~mask;
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return brcmstb_gpio_priv_set_wake(priv, enable);
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}
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static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
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{
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struct brcmstb_gpio_priv *priv = data;
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if (!priv || irq != priv->parent_wake_irq)
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return IRQ_NONE;
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/* Nothing to do */
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return IRQ_HANDLED;
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}
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static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
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{
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struct brcmstb_gpio_priv *priv = bank->parent_priv;
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struct irq_domain *domain = priv->irq_domain;
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int hwbase = bank->gc.base - priv->gpio_base;
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unsigned long status;
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while ((status = brcmstb_gpio_get_active_irqs(bank))) {
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unsigned int offset;
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for_each_set_bit(offset, &status, 32) {
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if (offset >= bank->width)
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dev_warn(&priv->pdev->dev,
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"IRQ for invalid GPIO (bank=%d, offset=%d)\n",
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bank->id, offset);
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generic_handle_domain_irq(domain, hwbase + offset);
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}
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}
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}
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/* Each UPG GIO block has one IRQ for all banks */
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static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
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{
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struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct brcmstb_gpio_bank *bank;
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/* Interrupts weren't properly cleared during probe */
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BUG_ON(!priv || !chip);
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chained_irq_enter(chip, desc);
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list_for_each_entry(bank, &priv->bank_list, node)
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brcmstb_gpio_irq_bank_handler(bank);
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chained_irq_exit(chip, desc);
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}
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static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
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struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
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{
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struct brcmstb_gpio_bank *bank;
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int i = 0;
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/* banks are in descending order */
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list_for_each_entry_reverse(bank, &priv->bank_list, node) {
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i += bank->gc.ngpio;
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if (hwirq < i)
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return bank;
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}
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return NULL;
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}
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/*
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* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key brcmstb_gpio_irq_lock_class;
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static struct lock_class_key brcmstb_gpio_irq_request_class;
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static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct brcmstb_gpio_priv *priv = d->host_data;
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struct brcmstb_gpio_bank *bank =
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brcmstb_gpio_hwirq_to_bank(priv, hwirq);
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struct platform_device *pdev = priv->pdev;
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int ret;
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if (!bank)
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return -EINVAL;
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dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
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irq, (int)hwirq, bank->id);
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ret = irq_set_chip_data(irq, &bank->gc);
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if (ret < 0)
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return ret;
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irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
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&brcmstb_gpio_irq_request_class);
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irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
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irq_set_noprobe(irq);
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return 0;
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}
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static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
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.map = brcmstb_gpio_irq_map,
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.unmap = brcmstb_gpio_irq_unmap,
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.xlate = irq_domain_xlate_twocell,
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};
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/* Make sure that the number of banks matches up between properties */
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static int brcmstb_gpio_sanity_check_banks(struct device *dev,
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struct device_node *np, struct resource *res)
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{
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int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
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int num_banks =
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of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
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if (res_num_banks != num_banks) {
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dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
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res_num_banks, num_banks);
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return -EINVAL;
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} else {
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return 0;
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}
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}
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static int brcmstb_gpio_remove(struct platform_device *pdev)
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{
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struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
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struct brcmstb_gpio_bank *bank;
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int offset, ret = 0, virq;
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if (!priv) {
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dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
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return -EFAULT;
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}
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if (priv->parent_irq > 0)
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irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
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/* Remove all IRQ mappings and delete the domain */
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if (priv->irq_domain) {
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for (offset = 0; offset < priv->num_gpios; offset++) {
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virq = irq_find_mapping(priv->irq_domain, offset);
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irq_dispose_mapping(virq);
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}
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irq_domain_remove(priv->irq_domain);
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}
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|
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/*
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* You can lose return values below, but we report all errors, and it's
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* more important to actually perform all of the steps.
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*/
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list_for_each_entry(bank, &priv->bank_list, node)
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gpiochip_remove(&bank->gc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
|
|
const struct of_phandle_args *gpiospec, u32 *flags)
|
|
{
|
|
struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
|
|
struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
|
|
int offset;
|
|
|
|
if (gc->of_gpio_n_cells != 2) {
|
|
WARN_ON(1);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
|
|
return -EINVAL;
|
|
|
|
offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
|
|
if (offset >= gc->ngpio || offset < 0)
|
|
return -EINVAL;
|
|
|
|
if (unlikely(offset >= bank->width)) {
|
|
dev_warn_ratelimited(&priv->pdev->dev,
|
|
"Received request for invalid GPIO offset %d\n",
|
|
gpiospec->args[0]);
|
|
}
|
|
|
|
if (flags)
|
|
*flags = gpiospec->args[1];
|
|
|
|
return offset;
|
|
}
|
|
|
|
/* priv->parent_irq and priv->num_gpios must be set before calling */
|
|
static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
|
|
struct brcmstb_gpio_priv *priv)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
int err;
|
|
|
|
priv->irq_domain =
|
|
irq_domain_add_linear(np, priv->num_gpios,
|
|
&brcmstb_gpio_irq_domain_ops,
|
|
priv);
|
|
if (!priv->irq_domain) {
|
|
dev_err(dev, "Couldn't allocate IRQ domain\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (of_property_read_bool(np, "wakeup-source")) {
|
|
priv->parent_wake_irq = platform_get_irq(pdev, 1);
|
|
if (priv->parent_wake_irq < 0) {
|
|
priv->parent_wake_irq = 0;
|
|
dev_warn(dev,
|
|
"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
|
|
} else {
|
|
/*
|
|
* Set wakeup capability so we can process boot-time
|
|
* "wakeups" (e.g., from S5 cold boot)
|
|
*/
|
|
device_set_wakeup_capable(dev, true);
|
|
device_wakeup_enable(dev);
|
|
err = devm_request_irq(dev, priv->parent_wake_irq,
|
|
brcmstb_gpio_wake_irq_handler,
|
|
IRQF_SHARED,
|
|
"brcmstb-gpio-wake", priv);
|
|
|
|
if (err < 0) {
|
|
dev_err(dev, "Couldn't request wake IRQ");
|
|
goto out_free_domain;
|
|
}
|
|
}
|
|
}
|
|
|
|
priv->irq_chip.name = dev_name(dev);
|
|
priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
|
|
priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
|
|
priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
|
|
priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
|
|
priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
|
|
|
|
if (priv->parent_wake_irq)
|
|
priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
|
|
|
|
irq_set_chained_handler_and_data(priv->parent_irq,
|
|
brcmstb_gpio_irq_handler, priv);
|
|
irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
|
|
|
|
return 0;
|
|
|
|
out_free_domain:
|
|
irq_domain_remove(priv->irq_domain);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
|
|
struct brcmstb_gpio_bank *bank)
|
|
{
|
|
struct gpio_chip *gc = &bank->gc;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < GIO_REG_STAT; i++)
|
|
bank->saved_regs[i] = gc->read_reg(priv->reg_base +
|
|
GIO_BANK_OFF(bank->id, i));
|
|
}
|
|
|
|
static void brcmstb_gpio_quiesce(struct device *dev, bool save)
|
|
{
|
|
struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
|
|
struct brcmstb_gpio_bank *bank;
|
|
struct gpio_chip *gc;
|
|
u32 imask;
|
|
|
|
/* disable non-wake interrupt */
|
|
if (priv->parent_irq >= 0)
|
|
disable_irq(priv->parent_irq);
|
|
|
|
list_for_each_entry(bank, &priv->bank_list, node) {
|
|
gc = &bank->gc;
|
|
|
|
if (save)
|
|
brcmstb_gpio_bank_save(priv, bank);
|
|
|
|
/* Unmask GPIOs which have been flagged as wake-up sources */
|
|
if (priv->parent_wake_irq)
|
|
imask = bank->wake_active;
|
|
else
|
|
imask = 0;
|
|
gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
|
|
imask);
|
|
}
|
|
}
|
|
|
|
static void brcmstb_gpio_shutdown(struct platform_device *pdev)
|
|
{
|
|
/* Enable GPIO for S5 cold boot */
|
|
brcmstb_gpio_quiesce(&pdev->dev, false);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
|
|
struct brcmstb_gpio_bank *bank)
|
|
{
|
|
struct gpio_chip *gc = &bank->gc;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < GIO_REG_STAT; i++)
|
|
gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
|
|
bank->saved_regs[i]);
|
|
}
|
|
|
|
static int brcmstb_gpio_suspend(struct device *dev)
|
|
{
|
|
brcmstb_gpio_quiesce(dev, true);
|
|
return 0;
|
|
}
|
|
|
|
static int brcmstb_gpio_resume(struct device *dev)
|
|
{
|
|
struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
|
|
struct brcmstb_gpio_bank *bank;
|
|
bool need_wakeup_event = false;
|
|
|
|
list_for_each_entry(bank, &priv->bank_list, node) {
|
|
need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
|
|
brcmstb_gpio_bank_restore(priv, bank);
|
|
}
|
|
|
|
if (priv->parent_wake_irq && need_wakeup_event)
|
|
pm_wakeup_event(dev, 0);
|
|
|
|
/* enable non-wake interrupt */
|
|
if (priv->parent_irq >= 0)
|
|
enable_irq(priv->parent_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define brcmstb_gpio_suspend NULL
|
|
#define brcmstb_gpio_resume NULL
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
|
|
.suspend_noirq = brcmstb_gpio_suspend,
|
|
.resume_noirq = brcmstb_gpio_resume,
|
|
};
|
|
|
|
static int brcmstb_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
void __iomem *reg_base;
|
|
struct brcmstb_gpio_priv *priv;
|
|
struct resource *res;
|
|
struct property *prop;
|
|
const __be32 *p;
|
|
u32 bank_width;
|
|
int num_banks = 0;
|
|
int err;
|
|
static int gpio_base;
|
|
unsigned long flags = 0;
|
|
bool need_wakeup_event = false;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, priv);
|
|
INIT_LIST_HEAD(&priv->bank_list);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
reg_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(reg_base))
|
|
return PTR_ERR(reg_base);
|
|
|
|
priv->gpio_base = gpio_base;
|
|
priv->reg_base = reg_base;
|
|
priv->pdev = pdev;
|
|
|
|
if (of_property_read_bool(np, "interrupt-controller")) {
|
|
priv->parent_irq = platform_get_irq(pdev, 0);
|
|
if (priv->parent_irq <= 0)
|
|
return -ENOENT;
|
|
} else {
|
|
priv->parent_irq = -ENOENT;
|
|
}
|
|
|
|
if (brcmstb_gpio_sanity_check_banks(dev, np, res))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* MIPS endianness is configured by boot strap, which also reverses all
|
|
* bus endianness (i.e., big-endian CPU + big endian bus ==> native
|
|
* endian I/O).
|
|
*
|
|
* Other architectures (e.g., ARM) either do not support big endian, or
|
|
* else leave I/O in little endian mode.
|
|
*/
|
|
#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
|
|
flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
|
|
#endif
|
|
|
|
of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
|
|
bank_width) {
|
|
struct brcmstb_gpio_bank *bank;
|
|
struct gpio_chip *gc;
|
|
|
|
/*
|
|
* If bank_width is 0, then there is an empty bank in the
|
|
* register block. Special handling for this case.
|
|
*/
|
|
if (bank_width == 0) {
|
|
dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
|
|
num_banks);
|
|
num_banks++;
|
|
gpio_base += MAX_GPIO_PER_BANK;
|
|
continue;
|
|
}
|
|
|
|
bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
|
|
if (!bank) {
|
|
err = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
bank->parent_priv = priv;
|
|
bank->id = num_banks;
|
|
if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
|
|
dev_err(dev, "Invalid bank width %d\n", bank_width);
|
|
err = -EINVAL;
|
|
goto fail;
|
|
} else {
|
|
bank->width = bank_width;
|
|
}
|
|
|
|
/*
|
|
* Regs are 4 bytes wide, have data reg, no set/clear regs,
|
|
* and direction bits have 0 = output and 1 = input
|
|
*/
|
|
gc = &bank->gc;
|
|
err = bgpio_init(gc, dev, 4,
|
|
reg_base + GIO_DATA(bank->id),
|
|
NULL, NULL, NULL,
|
|
reg_base + GIO_IODIR(bank->id), flags);
|
|
if (err) {
|
|
dev_err(dev, "bgpio_init() failed\n");
|
|
goto fail;
|
|
}
|
|
|
|
gc->owner = THIS_MODULE;
|
|
gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
|
|
if (!gc->label) {
|
|
err = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
gc->base = gpio_base;
|
|
gc->of_gpio_n_cells = 2;
|
|
gc->of_xlate = brcmstb_gpio_of_xlate;
|
|
/* not all ngpio lines are valid, will use bank width later */
|
|
gc->ngpio = MAX_GPIO_PER_BANK;
|
|
gc->offset = bank->id * MAX_GPIO_PER_BANK;
|
|
if (priv->parent_irq > 0)
|
|
gc->to_irq = brcmstb_gpio_to_irq;
|
|
|
|
/*
|
|
* Mask all interrupts by default, since wakeup interrupts may
|
|
* be retained from S5 cold boot
|
|
*/
|
|
need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
|
|
gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
|
|
|
|
err = gpiochip_add_data(gc, bank);
|
|
if (err) {
|
|
dev_err(dev, "Could not add gpiochip for bank %d\n",
|
|
bank->id);
|
|
goto fail;
|
|
}
|
|
gpio_base += gc->ngpio;
|
|
|
|
dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
|
|
gc->base, gc->ngpio, bank->width);
|
|
|
|
/* Everything looks good, so add bank to list */
|
|
list_add(&bank->node, &priv->bank_list);
|
|
|
|
num_banks++;
|
|
}
|
|
|
|
priv->num_gpios = gpio_base - priv->gpio_base;
|
|
if (priv->parent_irq > 0) {
|
|
err = brcmstb_gpio_irq_setup(pdev, priv);
|
|
if (err)
|
|
goto fail;
|
|
}
|
|
|
|
if (priv->parent_wake_irq && need_wakeup_event)
|
|
pm_wakeup_event(dev, 0);
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
(void) brcmstb_gpio_remove(pdev);
|
|
return err;
|
|
}
|
|
|
|
static const struct of_device_id brcmstb_gpio_of_match[] = {
|
|
{ .compatible = "brcm,brcmstb-gpio" },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
|
|
|
|
static struct platform_driver brcmstb_gpio_driver = {
|
|
.driver = {
|
|
.name = "brcmstb-gpio",
|
|
.of_match_table = brcmstb_gpio_of_match,
|
|
.pm = &brcmstb_gpio_pm_ops,
|
|
},
|
|
.probe = brcmstb_gpio_probe,
|
|
.remove = brcmstb_gpio_remove,
|
|
.shutdown = brcmstb_gpio_shutdown,
|
|
};
|
|
module_platform_driver(brcmstb_gpio_driver);
|
|
|
|
MODULE_AUTHOR("Gregory Fong");
|
|
MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
|
|
MODULE_LICENSE("GPL v2");
|