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527d147074
We add device tree files for a couple of additional SoCs in various areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for networking,
Amlogic A113D for audio, and Renesas R-Car V3M for automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX, Amlogic
and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues that
the latest version of 'dtc' now warns about. Unfortunately there is still
a lot left to do.
A rework of the ARM foundation model introduced several new files
for common variations of the model.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"We add device tree files for a couple of additional SoCs in various
areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for
networking, Amlogic A113D for audio, and Renesas R-Car V3M for
automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX,
Amlogic and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues
that the latest version of 'dtc' now warns about. Unfortunately there
is still a lot left to do.
A rework of the ARM foundation model introduced several new files for
common variations of the model"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits)
arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
dt-bindings: bus: Add documentation for the Technologic Systems NBUS
arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
ARM: dts: owl-s500: Add CubieBoard6
dt-bindings: arm: actions: Add CubieBoard6
ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock
ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
arm: dts: mt7623: remove unused compatible string for pio node
arm: dts: mt7623: update usb related nodes
arm: dts: mt7623: update crypto node
ARM: dts: sun8i: a711: Enable USB OTG
ARM: dts: sun8i: a711: Add regulator support
ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
ARM: dts: sunxi: Add dtsi for AXP81x PMIC
arm64: dts: allwinner: H5: Restore EMAC changes
...
807 lines
18 KiB
Plaintext
807 lines
18 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/include/ "skeleton.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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compatible = "marvell,dove";
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model = "Marvell Armada 88AP510 SoC";
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interrupt-parent = <&intc>;
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "marvell,pj4a", "marvell,sheeva-v7";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <0>;
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};
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};
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l2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0>;
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};
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gpu-subsystem {
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compatible = "marvell,dove-gpu-subsystem";
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cores = <&gpu>;
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status = "disabled";
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};
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i2c-mux {
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compatible = "i2c-mux-pinctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c>;
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pinctrl-names = "i2c0", "i2c1", "i2c2";
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pinctrl-0 = <&pmx_i2cmux_0>;
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pinctrl-1 = <&pmx_i2cmux_1>;
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pinctrl-2 = <&pmx_i2cmux_2>;
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i2c0: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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};
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i2c1: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Requires pmx_i2c1 on i2c controller node */
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status = "disabled";
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};
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i2c2: i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Requires pmx_i2c2 on i2c controller node */
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status = "disabled";
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};
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};
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mbus {
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compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
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pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
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MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
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MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
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MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
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MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
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pcie: pcie {
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compatible = "marvell,dove-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&intc>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
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0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
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0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
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0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
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0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
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0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
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pcie0: pcie@1 {
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device_type = "pci";
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status = "disabled";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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clocks = <&gate_clk 4>;
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marvell,pcie-port = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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bus-range = <0x00 0xff>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 16>;
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};
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pcie1: pcie@2 {
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device_type = "pci";
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status = "disabled";
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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clocks = <&gate_clk 5>;
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marvell,pcie-port = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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bus-range = <0x00 0xff>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 18>;
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};
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};
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
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0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
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0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
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0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
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spi0: spi-ctrl@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <6>;
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reg = <0x10600 0x28>;
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clocks = <&core_clk 0>;
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pinctrl-0 = <&pmx_spi0>;
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pinctrl-names = "default";
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status = "disabled";
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};
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i2c: i2c-ctrl@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11>;
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clock-frequency = <400000>;
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timeout-ms = <1000>;
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clocks = <&core_clk 0>;
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status = "okay";
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};
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uart0: serial@12000 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <7>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <8>;
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clocks = <&core_clk 0>;
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pinctrl-0 = <&pmx_uart1>;
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pinctrl-names = "default";
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status = "disabled";
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};
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uart2: serial@12200 {
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compatible = "ns16550a";
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reg = <0x12200 0x100>;
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reg-shift = <2>;
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interrupts = <9>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "ns16550a";
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reg = <0x12300 0x100>;
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reg-shift = <2>;
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interrupts = <10>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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spi1: spi-ctrl@14600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <5>;
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reg = <0x14600 0x28>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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mbusc: mbus-ctrl@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x80>, <0x800100 0x8>;
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};
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sysc: system-ctrl@20000 {
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compatible = "marvell,orion-system-controller";
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reg = <0x20000 0x110>;
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};
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bridge_intc: bridge-interrupt-ctrl@20110 {
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compatible = "marvell,orion-bridge-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20110 0x8>;
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interrupts = <0>;
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marvell,#interrupts = <5>;
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};
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intc: main-interrupt-ctrl@20200 {
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compatible = "marvell,orion-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20200 0x10>, <0x20210 0x10>;
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};
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timer: timer@20300 {
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compatible = "marvell,orion-timer";
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reg = <0x20300 0x20>;
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interrupt-parent = <&bridge_intc>;
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interrupts = <1>, <2>;
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clocks = <&core_clk 0>;
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};
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watchdog@20300 {
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compatible = "marvell,orion-wdt";
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reg = <0x20300 0x28>, <0x20108 0x4>;
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interrupt-parent = <&bridge_intc>;
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interrupts = <3>;
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clocks = <&core_clk 0>;
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};
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crypto: crypto-engine@30000 {
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compatible = "marvell,dove-crypto";
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reg = <0x30000 0x10000>;
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reg-names = "regs";
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interrupts = <31>;
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clocks = <&gate_clk 15>;
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marvell,crypto-srams = <&crypto_sram>;
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marvell,crypto-sram-size = <0x800>;
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status = "okay";
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};
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ehci0: usb-host@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <24>;
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clocks = <&gate_clk 0>;
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status = "okay";
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};
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ehci1: usb-host@51000 {
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compatible = "marvell,orion-ehci";
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reg = <0x51000 0x1000>;
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interrupts = <25>;
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clocks = <&gate_clk 1>;
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status = "okay";
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};
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xor0: dma-engine@60800 {
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compatible = "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60a00 0x100>;
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clocks = <&gate_clk 23>;
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status = "okay";
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channel0 {
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interrupts = <39>;
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dmacap,memcpy;
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dmacap,xor;
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};
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channel1 {
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interrupts = <40>;
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dmacap,memcpy;
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dmacap,xor;
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};
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};
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xor1: dma-engine@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gate_clk 24>;
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status = "okay";
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channel0 {
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interrupts = <42>;
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dmacap,memcpy;
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dmacap,xor;
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};
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channel1 {
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interrupts = <43>;
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dmacap,memcpy;
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dmacap,xor;
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};
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};
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sdio1: sdio-host@90000 {
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compatible = "marvell,dove-sdhci";
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reg = <0x90000 0x100>;
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interrupts = <36>, <38>;
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clocks = <&gate_clk 9>;
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pinctrl-0 = <&pmx_sdio1>;
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pinctrl-names = "default";
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status = "disabled";
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};
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|
|
eth: ethernet-ctrl@72000 {
|
|
compatible = "marvell,orion-eth";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x72000 0x4000>;
|
|
clocks = <&gate_clk 2>;
|
|
marvell,tx-checksum-limit = <1600>;
|
|
status = "disabled";
|
|
|
|
ethernet-port@0 {
|
|
compatible = "marvell,orion-eth-port";
|
|
reg = <0>;
|
|
interrupts = <29>;
|
|
/* overwrite MAC address in bootloader */
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
phy-handle = <ðphy>;
|
|
};
|
|
};
|
|
|
|
mdio: mdio-bus@72004 {
|
|
compatible = "marvell,orion-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x72004 0x84>;
|
|
interrupts = <30>;
|
|
clocks = <&gate_clk 2>;
|
|
status = "disabled";
|
|
|
|
ethphy: ethernet-phy {
|
|
/* set phy address in board file */
|
|
};
|
|
};
|
|
|
|
sdio0: sdio-host@92000 {
|
|
compatible = "marvell,dove-sdhci";
|
|
reg = <0x92000 0x100>;
|
|
interrupts = <35>, <37>;
|
|
clocks = <&gate_clk 8>;
|
|
pinctrl-0 = <&pmx_sdio0>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
sata0: sata-host@a0000 {
|
|
compatible = "marvell,orion-sata";
|
|
reg = <0xa0000 0x2400>;
|
|
interrupts = <62>;
|
|
clocks = <&gate_clk 3>;
|
|
phys = <&sata_phy0>;
|
|
phy-names = "port0";
|
|
nr-ports = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata_phy0: sata-phy@a2000 {
|
|
compatible = "marvell,mvebu-sata-phy";
|
|
reg = <0xa2000 0x0334>;
|
|
clocks = <&gate_clk 3>;
|
|
clock-names = "sata";
|
|
#phy-cells = <0>;
|
|
status = "ok";
|
|
};
|
|
|
|
audio0: audio-controller@b0000 {
|
|
compatible = "marvell,dove-audio";
|
|
reg = <0xb0000 0x2210>;
|
|
interrupts = <19>, <20>;
|
|
clocks = <&gate_clk 12>;
|
|
clock-names = "internal";
|
|
status = "disabled";
|
|
};
|
|
|
|
audio1: audio-controller@b4000 {
|
|
compatible = "marvell,dove-audio";
|
|
reg = <0xb4000 0x2210>;
|
|
interrupts = <21>, <22>;
|
|
clocks = <&gate_clk 13>;
|
|
clock-names = "internal";
|
|
status = "disabled";
|
|
};
|
|
|
|
pmu: power-management@d0000 {
|
|
compatible = "marvell,dove-pmu", "simple-bus";
|
|
reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
|
|
ranges = <0x00000000 0x000d0000 0x8000
|
|
0x00008000 0x000d8000 0x8000>;
|
|
interrupts = <33>;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
#interrupt-cells = <1>;
|
|
#reset-cells = <1>;
|
|
|
|
domains {
|
|
vpu_domain: vpu-domain {
|
|
#power-domain-cells = <0>;
|
|
marvell,pmu_pwr_mask = <0x00000008>;
|
|
marvell,pmu_iso_mask = <0x00000001>;
|
|
resets = <&pmu 16>;
|
|
};
|
|
|
|
gpu_domain: gpu-domain {
|
|
#power-domain-cells = <0>;
|
|
marvell,pmu_pwr_mask = <0x00000004>;
|
|
marvell,pmu_iso_mask = <0x00000002>;
|
|
resets = <&pmu 18>;
|
|
};
|
|
};
|
|
|
|
thermal: thermal-diode@1c {
|
|
compatible = "marvell,dove-thermal";
|
|
reg = <0x001c 0x0c>, <0x005c 0x08>;
|
|
};
|
|
|
|
gate_clk: clock-gating-ctrl@38 {
|
|
compatible = "marvell,dove-gating-clock";
|
|
reg = <0x0038 0x4>;
|
|
clocks = <&core_clk 0>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
divider_clk: core-clock@64 {
|
|
compatible = "marvell,dove-divider-clock";
|
|
reg = <0x0064 0x8>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pinctrl: pin-ctrl@200 {
|
|
compatible = "marvell,dove-pinctrl";
|
|
reg = <0x0200 0x14>,
|
|
<0x0440 0x04>;
|
|
clocks = <&gate_clk 22>;
|
|
|
|
pmx_gpio_0: pmx-gpio-0 {
|
|
marvell,pins = "mpp0";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_1: pmx-gpio-1 {
|
|
marvell,pins = "mpp1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_2: pmx-gpio-2 {
|
|
marvell,pins = "mpp2";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_3: pmx-gpio-3 {
|
|
marvell,pins = "mpp3";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_4: pmx-gpio-4 {
|
|
marvell,pins = "mpp4";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_5: pmx-gpio-5 {
|
|
marvell,pins = "mpp5";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_6: pmx-gpio-6 {
|
|
marvell,pins = "mpp6";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_7: pmx-gpio-7 {
|
|
marvell,pins = "mpp7";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_8: pmx-gpio-8 {
|
|
marvell,pins = "mpp8";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_9: pmx-gpio-9 {
|
|
marvell,pins = "mpp9";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_pcie1_clkreq: pmx-pcie1-clkreq {
|
|
marvell,pins = "mpp9";
|
|
marvell,function = "pex1";
|
|
};
|
|
|
|
pmx_gpio_10: pmx-gpio-10 {
|
|
marvell,pins = "mpp10";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_11: pmx-gpio-11 {
|
|
marvell,pins = "mpp11";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_pcie0_clkreq: pmx-pcie0-clkreq {
|
|
marvell,pins = "mpp11";
|
|
marvell,function = "pex0";
|
|
};
|
|
|
|
pmx_gpio_12: pmx-gpio-12 {
|
|
marvell,pins = "mpp12";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_13: pmx-gpio-13 {
|
|
marvell,pins = "mpp13";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_audio1_extclk: pmx-audio1-extclk {
|
|
marvell,pins = "mpp13";
|
|
marvell,function = "audio1";
|
|
};
|
|
|
|
pmx_gpio_14: pmx-gpio-14 {
|
|
marvell,pins = "mpp14";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_15: pmx-gpio-15 {
|
|
marvell,pins = "mpp15";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_16: pmx-gpio-16 {
|
|
marvell,pins = "mpp16";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_17: pmx-gpio-17 {
|
|
marvell,pins = "mpp17";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_18: pmx-gpio-18 {
|
|
marvell,pins = "mpp18";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_19: pmx-gpio-19 {
|
|
marvell,pins = "mpp19";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_20: pmx-gpio-20 {
|
|
marvell,pins = "mpp20";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_gpio_21: pmx-gpio-21 {
|
|
marvell,pins = "mpp21";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_camera: pmx-camera {
|
|
marvell,pins = "mpp_camera";
|
|
marvell,function = "camera";
|
|
};
|
|
|
|
pmx_camera_gpio: pmx-camera-gpio {
|
|
marvell,pins = "mpp_camera";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_sdio0: pmx-sdio0 {
|
|
marvell,pins = "mpp_sdio0";
|
|
marvell,function = "sdio0";
|
|
};
|
|
|
|
pmx_sdio0_gpio: pmx-sdio0-gpio {
|
|
marvell,pins = "mpp_sdio0";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_sdio1: pmx-sdio1 {
|
|
marvell,pins = "mpp_sdio1";
|
|
marvell,function = "sdio1";
|
|
};
|
|
|
|
pmx_sdio1_gpio: pmx-sdio1-gpio {
|
|
marvell,pins = "mpp_sdio1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_audio1_gpio: pmx-audio1-gpio {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "i2s1/spdifo";
|
|
};
|
|
|
|
pmx_spi0: pmx-spi0 {
|
|
marvell,pins = "mpp_spi0";
|
|
marvell,function = "spi0";
|
|
};
|
|
|
|
pmx_spi0_gpio: pmx-spi0-gpio {
|
|
marvell,pins = "mpp_spi0";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_spi1_4_7: pmx-spi1-4-7 {
|
|
marvell,pins = "mpp4", "mpp5",
|
|
"mpp6", "mpp7";
|
|
marvell,function = "spi1";
|
|
};
|
|
|
|
pmx_spi1_20_23: pmx-spi1-20-23 {
|
|
marvell,pins = "mpp20", "mpp21",
|
|
"mpp22", "mpp23";
|
|
marvell,function = "spi1";
|
|
};
|
|
|
|
pmx_uart1: pmx-uart1 {
|
|
marvell,pins = "mpp_uart1";
|
|
marvell,function = "uart1";
|
|
};
|
|
|
|
pmx_uart1_gpio: pmx-uart1-gpio {
|
|
marvell,pins = "mpp_uart1";
|
|
marvell,function = "gpio";
|
|
};
|
|
|
|
pmx_nand: pmx-nand {
|
|
marvell,pins = "mpp_nand";
|
|
marvell,function = "nand";
|
|
};
|
|
|
|
pmx_nand_gpo: pmx-nand-gpo {
|
|
marvell,pins = "mpp_nand";
|
|
marvell,function = "gpo";
|
|
};
|
|
|
|
pmx_i2c1: pmx-i2c1 {
|
|
marvell,pins = "mpp17", "mpp19";
|
|
marvell,function = "twsi";
|
|
};
|
|
|
|
pmx_i2c2: pmx-i2c2 {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "twsi";
|
|
};
|
|
|
|
pmx_ssp_i2c2: pmx-ssp-i2c2 {
|
|
marvell,pins = "mpp_audio1";
|
|
marvell,function = "ssp/twsi";
|
|
};
|
|
|
|
pmx_i2cmux_0: pmx-i2cmux-0 {
|
|
marvell,pins = "twsi";
|
|
marvell,function = "twsi-opt1";
|
|
};
|
|
|
|
pmx_i2cmux_1: pmx-i2cmux-1 {
|
|
marvell,pins = "twsi";
|
|
marvell,function = "twsi-opt2";
|
|
};
|
|
|
|
pmx_i2cmux_2: pmx-i2cmux-2 {
|
|
marvell,pins = "twsi";
|
|
marvell,function = "twsi-opt3";
|
|
};
|
|
};
|
|
|
|
core_clk: core-clocks@214 {
|
|
compatible = "marvell,dove-core-clock";
|
|
reg = <0x0214 0x4>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpio0: gpio-ctrl@400 {
|
|
compatible = "marvell,orion-gpio";
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0x0400 0x20>;
|
|
ngpios = <32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <12>, <13>, <14>, <60>;
|
|
};
|
|
|
|
gpio1: gpio-ctrl@420 {
|
|
compatible = "marvell,orion-gpio";
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0x0420 0x20>;
|
|
ngpios = <32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <61>;
|
|
};
|
|
|
|
rtc: real-time-clock@8500 {
|
|
compatible = "marvell,orion-rtc";
|
|
reg = <0x8500 0x20>;
|
|
interrupts = <5>;
|
|
};
|
|
};
|
|
|
|
gconf: global-config@e802c {
|
|
compatible = "marvell,dove-global-config",
|
|
"syscon";
|
|
reg = <0xe802c 0x14>;
|
|
};
|
|
|
|
gpio2: gpio-ctrl@e8400 {
|
|
compatible = "marvell,orion-gpio";
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0xe8400 0x0c>;
|
|
ngpios = <8>;
|
|
};
|
|
|
|
lcd1: lcd-controller@810000 {
|
|
compatible = "marvell,dove-lcd";
|
|
reg = <0x810000 0x1000>;
|
|
interrupts = <46>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lcd0: lcd-controller@820000 {
|
|
compatible = "marvell,dove-lcd";
|
|
reg = <0x820000 0x1000>;
|
|
interrupts = <47>;
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto_sram: sa-sram@ffffe000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xffffe000 0x800>;
|
|
clocks = <&gate_clk 15>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
|
|
gpu: gpu@840000 {
|
|
clocks = <÷r_clk 1>;
|
|
clock-names = "core";
|
|
compatible = "vivante,gc";
|
|
interrupts = <48>;
|
|
power-domains = <&gpu_domain>;
|
|
reg = <0x840000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|