mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-29 22:14:41 +08:00
43d9af3f19
For consistency with all other serial pins, add this pullup. It also prevents the signal from floating and so consuming a useless extra amount of power in crowbarred state if nothing is connected to RX. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
970 lines
25 KiB
Plaintext
970 lines
25 KiB
Plaintext
/*
|
|
* at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
|
|
*
|
|
* Copyright (C) 2011 Atmel,
|
|
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
|
|
* 2012 Joachim Eastwood <manabian@gmail.com>
|
|
*
|
|
* Based on at91sam9260.dtsi
|
|
*
|
|
* Licensed under GPLv2 or later.
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include <dt-bindings/pinctrl/at91.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/clock/at91.h>
|
|
|
|
/ {
|
|
model = "Atmel AT91RM9200 family SoC";
|
|
compatible = "atmel,at91rm9200";
|
|
interrupt-parent = <&aic>;
|
|
|
|
aliases {
|
|
serial0 = &dbgu;
|
|
serial1 = &usart0;
|
|
serial2 = &usart1;
|
|
serial3 = &usart2;
|
|
serial4 = &usart3;
|
|
gpio0 = &pioA;
|
|
gpio1 = &pioB;
|
|
gpio2 = &pioC;
|
|
gpio3 = &pioD;
|
|
tcb0 = &tcb0;
|
|
tcb1 = &tcb1;
|
|
i2c0 = &i2c0;
|
|
ssc0 = &ssc0;
|
|
ssc1 = &ssc1;
|
|
ssc2 = &ssc2;
|
|
};
|
|
cpus {
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
|
|
cpu {
|
|
compatible = "arm,arm920t";
|
|
device_type = "cpu";
|
|
};
|
|
};
|
|
|
|
memory {
|
|
reg = <0x20000000 0x04000000>;
|
|
};
|
|
|
|
clocks {
|
|
slow_xtal: slow_xtal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
main_xtal: main_xtal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|
|
|
|
sram: sram@200000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x00200000 0x4000>;
|
|
};
|
|
|
|
ahb {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
apb {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
aic: interrupt-controller@fffff000 {
|
|
#interrupt-cells = <3>;
|
|
compatible = "atmel,at91rm9200-aic";
|
|
interrupt-controller;
|
|
reg = <0xfffff000 0x200>;
|
|
atmel,external-irqs = <25 26 27 28 29 30 31>;
|
|
};
|
|
|
|
ramc0: ramc@ffffff00 {
|
|
compatible = "atmel,at91rm9200-sdramc", "syscon";
|
|
reg = <0xffffff00 0x100>;
|
|
};
|
|
|
|
pmc: pmc@fffffc00 {
|
|
compatible = "atmel,at91rm9200-pmc", "syscon";
|
|
reg = <0xfffffc00 0x100>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
|
|
main_osc: main_osc {
|
|
compatible = "atmel,at91rm9200-clk-main-osc";
|
|
#clock-cells = <0>;
|
|
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
|
|
clocks = <&main_xtal>;
|
|
};
|
|
|
|
main: mainck {
|
|
compatible = "atmel,at91rm9200-clk-main";
|
|
#clock-cells = <0>;
|
|
clocks = <&main_osc>;
|
|
};
|
|
|
|
plla: pllack {
|
|
compatible = "atmel,at91rm9200-clk-pll";
|
|
#clock-cells = <0>;
|
|
interrupts-extended = <&pmc AT91_PMC_LOCKA>;
|
|
clocks = <&main>;
|
|
reg = <0>;
|
|
atmel,clk-input-range = <1000000 32000000>;
|
|
#atmel,pll-clk-output-range-cells = <3>;
|
|
atmel,pll-clk-output-ranges = <80000000 160000000 0>,
|
|
<150000000 180000000 2>;
|
|
};
|
|
|
|
pllb: pllbck {
|
|
compatible = "atmel,at91rm9200-clk-pll";
|
|
#clock-cells = <0>;
|
|
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
|
|
clocks = <&main>;
|
|
reg = <1>;
|
|
atmel,clk-input-range = <1000000 32000000>;
|
|
#atmel,pll-clk-output-range-cells = <3>;
|
|
atmel,pll-clk-output-ranges = <80000000 160000000 0>,
|
|
<150000000 180000000 2>;
|
|
};
|
|
|
|
mck: masterck {
|
|
compatible = "atmel,at91rm9200-clk-master";
|
|
#clock-cells = <0>;
|
|
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
|
|
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
|
atmel,clk-output-range = <0 80000000>;
|
|
atmel,clk-divisors = <1 2 3 4>;
|
|
};
|
|
|
|
usb: usbck {
|
|
compatible = "atmel,at91rm9200-clk-usb";
|
|
#clock-cells = <0>;
|
|
atmel,clk-divisors = <1 2 0 0>;
|
|
clocks = <&pllb>;
|
|
};
|
|
|
|
prog: progck {
|
|
compatible = "atmel,at91rm9200-clk-programmable";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
|
|
|
|
prog0: prog0 {
|
|
#clock-cells = <0>;
|
|
reg = <0>;
|
|
interrupts = <AT91_PMC_PCKRDY(0)>;
|
|
};
|
|
|
|
prog1: prog1 {
|
|
#clock-cells = <0>;
|
|
reg = <1>;
|
|
interrupts = <AT91_PMC_PCKRDY(1)>;
|
|
};
|
|
|
|
prog2: prog2 {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
interrupts = <AT91_PMC_PCKRDY(2)>;
|
|
};
|
|
|
|
prog3: prog3 {
|
|
#clock-cells = <0>;
|
|
reg = <3>;
|
|
interrupts = <AT91_PMC_PCKRDY(3)>;
|
|
};
|
|
};
|
|
|
|
systemck {
|
|
compatible = "atmel,at91rm9200-clk-system";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
udpck: udpck {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
uhpck: uhpck {
|
|
#clock-cells = <0>;
|
|
reg = <4>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
pck0: pck0 {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
clocks = <&prog0>;
|
|
};
|
|
|
|
pck1: pck1 {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
clocks = <&prog1>;
|
|
};
|
|
|
|
pck2: pck2 {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
clocks = <&prog2>;
|
|
};
|
|
|
|
pck3: pck3 {
|
|
#clock-cells = <0>;
|
|
reg = <11>;
|
|
clocks = <&prog3>;
|
|
};
|
|
};
|
|
|
|
periphck {
|
|
compatible = "atmel,at91rm9200-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mck>;
|
|
|
|
pioA_clk: pioA_clk {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
};
|
|
|
|
pioB_clk: pioB_clk {
|
|
#clock-cells = <0>;
|
|
reg = <3>;
|
|
};
|
|
|
|
pioC_clk: pioC_clk {
|
|
#clock-cells = <0>;
|
|
reg = <4>;
|
|
};
|
|
|
|
pioD_clk: pioD_clk {
|
|
#clock-cells = <0>;
|
|
reg = <5>;
|
|
};
|
|
|
|
usart0_clk: usart0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
};
|
|
|
|
usart1_clk: usart1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
};
|
|
|
|
usart2_clk: usart2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
};
|
|
|
|
usart3_clk: usart3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
};
|
|
|
|
mci0_clk: mci0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
};
|
|
|
|
udc_clk: udc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <11>;
|
|
};
|
|
|
|
twi0_clk: twi0_clk {
|
|
reg = <12>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
spi0_clk: spi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <13>;
|
|
};
|
|
|
|
ssc0_clk: ssc0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <14>;
|
|
};
|
|
|
|
ssc1_clk: ssc1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <15>;
|
|
};
|
|
|
|
ssc2_clk: ssc2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <16>;
|
|
};
|
|
|
|
tc0_clk: tc0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <17>;
|
|
};
|
|
|
|
tc1_clk: tc1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
};
|
|
|
|
tc2_clk: tc2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <19>;
|
|
};
|
|
|
|
tc3_clk: tc3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <20>;
|
|
};
|
|
|
|
tc4_clk: tc4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <21>;
|
|
};
|
|
|
|
tc5_clk: tc5_clk {
|
|
#clock-cells = <0>;
|
|
reg = <22>;
|
|
};
|
|
|
|
ohci_clk: ohci_clk {
|
|
#clock-cells = <0>;
|
|
reg = <23>;
|
|
};
|
|
|
|
macb0_clk: macb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <24>;
|
|
};
|
|
};
|
|
};
|
|
|
|
st: timer@fffffd00 {
|
|
compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
|
|
reg = <0xfffffd00 0x100>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&slow_xtal>;
|
|
|
|
watchdog {
|
|
compatible = "atmel,at91rm9200-wdt";
|
|
};
|
|
};
|
|
|
|
rtc: rtc@fffffe00 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xfffffe00 0x40>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&slow_xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@fffa0000 {
|
|
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xfffa0000 0x100>;
|
|
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
|
|
18 IRQ_TYPE_LEVEL_HIGH 0
|
|
19 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
|
|
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
|
|
};
|
|
|
|
tcb1: timer@fffa4000 {
|
|
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xfffa4000 0x100>;
|
|
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
|
|
21 IRQ_TYPE_LEVEL_HIGH 0
|
|
22 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>;
|
|
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
|
|
};
|
|
|
|
i2c0: i2c@fffb8000 {
|
|
compatible = "atmel,at91rm9200-i2c";
|
|
reg = <0xfffb8000 0x4000>;
|
|
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_twi>;
|
|
clocks = <&twi0_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@fffb4000 {
|
|
compatible = "atmel,hsmci";
|
|
reg = <0xfffb4000 0x4000>;
|
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&mci0_clk>;
|
|
clock-names = "mci_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssc0: ssc@fffd0000 {
|
|
compatible = "atmel,at91rm9200-ssc";
|
|
reg = <0xfffd0000 0x4000>;
|
|
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
|
clocks = <&ssc0_clk>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssc1: ssc@fffd4000 {
|
|
compatible = "atmel,at91rm9200-ssc";
|
|
reg = <0xfffd4000 0x4000>;
|
|
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
|
|
clocks = <&ssc1_clk>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssc2: ssc@fffd8000 {
|
|
compatible = "atmel,at91rm9200-ssc";
|
|
reg = <0xfffd8000 0x4000>;
|
|
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
|
|
clocks = <&ssc2_clk>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
macb0: ethernet@fffbc000 {
|
|
compatible = "cdns,at91rm9200-emac", "cdns,emac";
|
|
reg = <0xfffbc000 0x4000>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
phy-mode = "rmii";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_macb_rmii>;
|
|
clocks = <&macb0_clk>;
|
|
clock-names = "ether_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl@fffff400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
|
ranges = <0xfffff400 0xfffff400 0x800>;
|
|
|
|
atmel,mux-mask = <
|
|
/* A B */
|
|
0xffffffff 0xffffffff /* pioA */
|
|
0xffffffff 0x083fffff /* pioB */
|
|
0xffff3fff 0x00000000 /* pioC */
|
|
0x03ff87ff 0x0fffff80 /* pioD */
|
|
>;
|
|
|
|
/* shared pinctrl settings */
|
|
dbgu {
|
|
pinctrl_dbgu: dbgu-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
|
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
pinctrl_uart0: uart0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE
|
|
AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
pinctrl_uart0_cts: uart0_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
|
|
};
|
|
|
|
pinctrl_uart0_rts: uart0_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
pinctrl_uart1: uart1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
|
|
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
pinctrl_uart1_rts: uart1_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
|
|
};
|
|
|
|
pinctrl_uart1_cts: uart1_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
|
|
};
|
|
|
|
pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
|
|
AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
|
|
};
|
|
|
|
pinctrl_uart1_dcd: uart1_dcd-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
|
|
};
|
|
|
|
pinctrl_uart1_ri: uart1_ri-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
pinctrl_uart2: uart2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
|
AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_uart2_rts: uart2_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
|
|
};
|
|
|
|
pinctrl_uart2_cts: uart2_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
|
|
};
|
|
};
|
|
|
|
uart3 {
|
|
pinctrl_uart3: uart3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE
|
|
AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
pinctrl_uart3_rts: uart3_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
|
|
};
|
|
|
|
pinctrl_uart3_cts: uart3_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
|
|
};
|
|
};
|
|
|
|
nand {
|
|
pinctrl_nand: nand-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */
|
|
AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */
|
|
};
|
|
};
|
|
|
|
macb {
|
|
pinctrl_macb_rmii: macb_rmii-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */
|
|
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */
|
|
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
|
|
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
|
|
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
|
|
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
|
|
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
|
|
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
|
|
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
|
|
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
|
|
};
|
|
|
|
pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */
|
|
AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */
|
|
AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */
|
|
AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */
|
|
AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */
|
|
AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */
|
|
AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */
|
|
AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
|
|
};
|
|
};
|
|
|
|
mmc0 {
|
|
pinctrl_mmc0_clk: mmc0_clk-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
|
|
};
|
|
|
|
pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
|
|
AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
|
|
AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
|
|
AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
|
|
AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */
|
|
AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
|
|
AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */
|
|
};
|
|
};
|
|
|
|
ssc0 {
|
|
pinctrl_ssc0_tx: ssc0_tx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
|
|
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
|
|
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */
|
|
};
|
|
|
|
pinctrl_ssc0_rx: ssc0_rx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
|
|
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
|
|
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
|
|
};
|
|
};
|
|
|
|
ssc1 {
|
|
pinctrl_ssc1_tx: ssc1_tx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
|
|
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
|
|
AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
|
|
};
|
|
|
|
pinctrl_ssc1_rx: ssc1_rx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
|
|
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
|
|
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
|
|
};
|
|
};
|
|
|
|
ssc2 {
|
|
pinctrl_ssc2_tx: ssc2_tx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
|
|
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
|
|
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
|
|
};
|
|
|
|
pinctrl_ssc2_rx: ssc2_rx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
|
|
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
|
|
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
|
|
};
|
|
};
|
|
|
|
twi {
|
|
pinctrl_twi: twi-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */
|
|
AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */
|
|
};
|
|
|
|
pinctrl_twi_gpio: twi_gpio-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
|
|
AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */
|
|
};
|
|
};
|
|
|
|
tcb0 {
|
|
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
|
atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
|
atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
|
atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
|
atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
|
atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
|
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
|
atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
|
atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
|
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
tcb1 {
|
|
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
|
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
|
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
|
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
|
atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
|
atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
|
atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
|
atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
|
atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
|
atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
pinctrl_spi0: spi0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
|
|
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
|
|
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
|
|
};
|
|
};
|
|
|
|
pioA: gpio@fffff400 {
|
|
compatible = "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff400 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioA_clk>;
|
|
};
|
|
|
|
pioB: gpio@fffff600 {
|
|
compatible = "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff600 0x200>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioB_clk>;
|
|
};
|
|
|
|
pioC: gpio@fffff800 {
|
|
compatible = "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff800 0x200>;
|
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioC_clk>;
|
|
};
|
|
|
|
pioD: gpio@fffffa00 {
|
|
compatible = "atmel,at91rm9200-gpio";
|
|
reg = <0xfffffa00 0x200>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioD_clk>;
|
|
};
|
|
};
|
|
|
|
dbgu: serial@fffff200 {
|
|
compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
|
|
reg = <0xfffff200 0x200>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_dbgu>;
|
|
clocks = <&mck>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart0: serial@fffc0000 {
|
|
compatible = "atmel,at91rm9200-usart";
|
|
reg = <0xfffc0000 0x200>;
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart0>;
|
|
clocks = <&usart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart1: serial@fffc4000 {
|
|
compatible = "atmel,at91rm9200-usart";
|
|
reg = <0xfffc4000 0x200>;
|
|
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
clocks = <&usart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart2: serial@fffc8000 {
|
|
compatible = "atmel,at91rm9200-usart";
|
|
reg = <0xfffc8000 0x200>;
|
|
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
clocks = <&usart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart3: serial@fffcc000 {
|
|
compatible = "atmel,at91rm9200-usart";
|
|
reg = <0xfffcc000 0x200>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
|
clocks = <&usart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: gadget@fffb0000 {
|
|
compatible = "atmel,at91rm9200-udc";
|
|
reg = <0xfffb0000 0x4000>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&udc_clk>, <&udpck>;
|
|
clock-names = "pclk", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@fffe0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xfffe0000 0x200>;
|
|
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi0>;
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
nand0: nand@40000000 {
|
|
compatible = "atmel,at91rm9200-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x40000000 0x10000000>;
|
|
atmel,nand-addr-offset = <21>;
|
|
atmel,nand-cmd-offset = <22>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
nand-ecc-mode = "soft";
|
|
gpios = <&pioC 2 GPIO_ACTIVE_HIGH
|
|
0
|
|
&pioB 1 GPIO_ACTIVE_HIGH
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb0: ohci@300000 {
|
|
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
|
reg = <0x00300000 0x100000>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
|
|
clock-names = "ohci_clk", "hclk", "uhpck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
i2c-gpio-0 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
|
|
&pioA 26 GPIO_ACTIVE_HIGH /* scl */
|
|
>;
|
|
i2c-gpio,sda-open-drain;
|
|
i2c-gpio,scl-open-drain;
|
|
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_twi_gpio>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|