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https://mirrors.bfsu.edu.cn/git/linux.git
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da7920e31d
- New board support: i.MX51 ZII RDU1, i.MX53 GE Healthcare PPD, i.MX6
TX modules for MB7 from Ka-Ro Electronics, i.MX6 Wandboard revd1
variants, i.MX6 LWN DISPLAY5 board, Pistachio i.MX6Q board, i.MX6SX
Vining-2000 board.
- Use the 'vpcie-supply' property for PCIe device for boards
imx6qdl-sabresd, imx6q-novena and imx6q-cm-fx6.
- A series from Jagan Teki to update imx6qdl-icore board with audio,
touch and CAN support.
- Switch to nvmem for accessing OCOTP from tempmon for i.MX6SX and add
tempmon support for i.MX6UL.
- A bunch of patches from Lothar Waßmann updating Ka-Ro i.MX28, i.MX53
and i.MX6 TX modules.
- Fix DTC warnings in i.MX device trees, dropping leading zeros from
unit address, correcting display nodes notation and display port
names, fixing nodes with unit name and no reg property.
- Other random device updates for various board support.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJZ7ypUAAoJEFBXWFqHsHzOpVkH/RsZ3IMg8O5tMO6uz1CNmutR
3EAXfBeQTnQZe2A/3XkDRpJWGiIniRSVAf6rYipmeyV9jV2Ff4vfiv5gnhg1ev+B
eV35W3gb3EclHKrHgHVMkfzWfNp63L1etdVFrY0QuMc0wQbch0TwO3TTPHpk0+AS
eauLOMY1qzRVnayzZ8IeTn++igsoj4KT1NmIprNKe66eDAOfWxO0IB26r0svKrhg
mIlqTUG1p6I/H8h6hQZuRJaLM9no3dHDcm7Scbf1y8Mvf5mPVTTHKXGLLyEVT/UB
SEWydfAt0VEAEA+Uk6pFJsrG1KRx0hwF46DHk2BXj7A1wxBsUIPnMSoMRWgGrZE=
=grKK
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Pull "i.MX device tree updates for 4.15" from Shawn Guo:
- New board support: i.MX51 ZII RDU1, i.MX53 GE Healthcare PPD, i.MX6
TX modules for MB7 from Ka-Ro Electronics, i.MX6 Wandboard revd1
variants, i.MX6 LWN DISPLAY5 board, Pistachio i.MX6Q board, i.MX6SX
Vining-2000 board.
- Use the 'vpcie-supply' property for PCIe device for boards
imx6qdl-sabresd, imx6q-novena and imx6q-cm-fx6.
- A series from Jagan Teki to update imx6qdl-icore board with audio,
touch and CAN support.
- Switch to nvmem for accessing OCOTP from tempmon for i.MX6SX and add
tempmon support for i.MX6UL.
- A bunch of patches from Lothar Waßmann updating Ka-Ro i.MX28, i.MX53
and i.MX6 TX modules.
- Fix DTC warnings in i.MX device trees, dropping leading zeros from
unit address, correcting display nodes notation and display port
names, fixing nodes with unit name and no reg property.
- Other random device updates for various board support.
* tag 'imx-dt-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (63 commits)
ARM: dts: imx53-tx53: fix interrupt flags
ARM: dts: imx28-tx28: fix interrupt flags
ARM: dts: display5: Device tree description of LWN's DISPLAY5 board
ARM: dts: imx53-qsb-common: Fix 'led_gpio7_7@0' node with unit name and no reg property
ARM: dts: imx53-m53evk: Fix 'led_gpio@0' node with unit name and no reg property
ARM: dts: imx53: Fix 'usbphy@x' node with unit name and no reg property
ARM: dts: imx51-ts4800: Fix 'port@0' node with unit name and no reg property
ARM: dts: imx51-apf51dev: Fix 'backlight@bl1' node with unit name and no reg property
ARM: dts: imx: add ZII RDU1 board
ARM: dts: imx: add support for TX6 modules on MB7 baseboard
ARM: dts: imx: add support for TX6QP
ARM: dts: imx6-tx6: add a .dtsi file for the MB7 baseboard
ARM: dts: imx6-tx6: move display configuration to .dtsi file
ARM: dts: imx6-tx6: add support for I2C bus recovery
ARM: dts: imx6-tx6: convert to using simple-audio-card
ARM: dts: imx6-tx6: specify ethernet phy reset post-delay
ARM: dts: imx6-tx6: improve ethernet related pinctrl setup
ARM: dts: imx6-tx6: add trickle-charge config for DS1339
ARM: dts: imx6-tx6: remove obsolete ipu1 alias
ARM: dts: imx6-tx6: remove obsolete eeti,egalax_ts
...
[arnd: made sure we have no new leading zeroes in unit address during merge]
972 lines
24 KiB
Plaintext
972 lines
24 KiB
Plaintext
/*
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* Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pwm/pwm.h>
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/ {
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aliases {
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can0 = &can2;
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can1 = &can1;
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display = &display;
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i2c0 = &i2c2;
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i2c1 = &i2c_gpio;
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i2c2 = &i2c1;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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lcdif_23bit_pins_a = &pinctrl_disp0_1;
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lcdif_24bit_pins_a = &pinctrl_disp0_2;
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pwm0 = &pwm5;
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reg_can_xcvr = ®_can_xcvr;
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serial2 = &uart5;
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serial4 = &uart3;
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spi0 = &ecspi2;
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spi1 = &spi_gpio;
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stk5led = &user_led;
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usbh1 = &usbotg2;
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usbotg = &usbotg1;
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};
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0 0>; /* will be filled by U-Boot */
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};
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clocks {
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mclk: mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd_rst>;
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enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
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pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
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power-supply = <®_lcd_pwr>;
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/*
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* a poor man's way to create a 1:1 relationship between
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* the PWM value and the actual duty cycle
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*/
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brightness-levels = < 0 1 2 3 4 5 6 7 8 9
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10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47 48 49
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50 51 52 53 54 55 56 57 58 59
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60 61 62 63 64 65 66 67 68 69
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70 71 72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87 88 89
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90 91 92 93 94 95 96 97 98 99
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100>;
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default-brightness-level = <50>;
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};
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i2c_gpio: i2c-gpio {
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compatible = "i2c-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c_gpio>;
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gpios = <
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&gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
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&gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
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>;
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clock-frequency = <400000>;
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status = "okay";
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ds1339: rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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status = "disabled";
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};
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};
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leds {
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compatible = "gpio-leds";
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user_led: user {
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label = "Heartbeat";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_led>;
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gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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reg_3v3_etn: regulator-3v3etn {
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compatible = "regulator-fixed";
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regulator-name = "3V3_ETN";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_etnphy_power>;
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gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_2v5: regulator-2v5 {
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compatible = "regulator-fixed";
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regulator-name = "2V5";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-always-on;
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};
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reg_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_can_xcvr: regulator-canxcvr {
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compatible = "regulator-fixed";
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regulator-name = "CAN XCVR";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan_xcvr>;
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gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
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};
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reg_lcd_pwr: regulator-lcdpwr {
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compatible = "regulator-fixed";
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regulator-name = "LCD POWER";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd_pwr>;
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gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_usbh1_vbus: regulator-usbh1vbus {
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compatible = "regulator-fixed";
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regulator-name = "usbh1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
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gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usbotg_vbus: regulator-usbotgvbus {
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compatible = "regulator-fixed";
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regulator-name = "usbotg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
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gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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spi_gpio: spi-gpio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "spi-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi_gpio>;
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gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
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gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
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gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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num-chipselects = <2>;
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cs-gpios = <
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&gpio1 29 GPIO_ACTIVE_HIGH
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&gpio1 10 GPIO_ACTIVE_HIGH
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>;
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status = "disabled";
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spi@0 {
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compatible = "spidev";
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reg = <0>;
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spi-max-frequency = <660000>;
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};
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spi@1 {
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compatible = "spidev";
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reg = <1>;
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spi-max-frequency = <660000>;
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};
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};
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sound {
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compatible = "karo,imx6ul-tx6ul-sgtl5000",
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"simple-audio-card";
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simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&codec_dai>;
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simple-audio-card,frame-master = <&codec_dai>;
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simple-audio-card,widgets =
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"Microphone", "Mic Jack",
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"Line", "Line In",
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"Line", "Line Out",
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"Headphone", "Headphone Jack";
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simple-audio-card,routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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cpu_dai: simple-audio-card,cpu {
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sound-dai = <&sai2>;
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};
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codec_dai: simple-audio-card,codec {
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sound-dai = <&sgtl5000>;
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};
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can_xcvr>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can_xcvr>;
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status = "okay";
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};
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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cs-gpios = <
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&gpio1 29 GPIO_ACTIVE_HIGH
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&gpio1 10 GPIO_ACTIVE_HIGH
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>;
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status = "disabled";
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spidev0: spi@0 {
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compatible = "spidev";
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reg = <0>;
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spi-max-frequency = <60000000>;
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};
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spidev1: spi@1 {
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compatible = "spidev";
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reg = <1>;
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spi-max-frequency = <60000000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
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phy-supply = <®_3v3_etn>;
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phy-handle = <&etnphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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etnphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_etnphy0_int>;
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interrupt-parent = <&gpio5>;
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
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status = "okay";
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};
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etnphy1: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_etnphy1_int>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
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status = "okay";
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
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phy-supply = <®_3v3_etn>;
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phy-handle = <&etnphy1>;
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status = "disabled";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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fsl,no-blockmark-swap;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <400000>;
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status = "okay";
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sgtl5000: codec@a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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#sound-dai-cells = <0>;
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VDDA-supply = <®_2v5>;
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VDDIO-supply = <®_3v3>;
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clocks = <&mclk>;
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};
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polytouch: polytouch@38 {
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compatible = "edt,edt-ft5x06";
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reg = <0x38>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_edt_ft5x06>;
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interrupt-parent = <&gpio5>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
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wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
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wakeup-source;
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};
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touchscreen: touchscreen@48 {
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compatible = "ti,tsc2007";
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reg = <0x48>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc2007>;
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interrupt-parent = <&gpio3>;
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interrupts = <26 IRQ_TYPE_NONE>;
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gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
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ti,x-plate-ohms = <660>;
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wakeup-source;
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};
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};
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&kpp {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_kpp>;
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|
/* sample keymap */
|
|
/* row/col 0..3 are mapped to KPP row/col 4..7 */
|
|
linux,keymap = <
|
|
MATRIX_KEY(4, 4, KEY_POWER)
|
|
MATRIX_KEY(4, 5, KEY_KP0)
|
|
MATRIX_KEY(4, 6, KEY_KP1)
|
|
MATRIX_KEY(4, 7, KEY_KP2)
|
|
MATRIX_KEY(5, 4, KEY_KP3)
|
|
MATRIX_KEY(5, 5, KEY_KP4)
|
|
MATRIX_KEY(5, 6, KEY_KP5)
|
|
MATRIX_KEY(5, 7, KEY_KP6)
|
|
MATRIX_KEY(6, 4, KEY_KP7)
|
|
MATRIX_KEY(6, 5, KEY_KP8)
|
|
MATRIX_KEY(6, 6, KEY_KP9)
|
|
>;
|
|
status = "okay";
|
|
};
|
|
|
|
&lcdif {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_disp0_1>;
|
|
lcd-supply = <®_lcd_pwr>;
|
|
display = <&display>;
|
|
status = "okay";
|
|
|
|
display: disp0 {
|
|
bits-per-pixel = <32>;
|
|
bus-width = <24>;
|
|
status = "okay";
|
|
|
|
display-timings {
|
|
VGA {
|
|
clock-frequency = <25200000>;
|
|
hactive = <640>;
|
|
vactive = <480>;
|
|
hback-porch = <48>;
|
|
hsync-len = <96>;
|
|
hfront-porch = <16>;
|
|
vback-porch = <31>;
|
|
vsync-len = <2>;
|
|
vfront-porch = <12>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <1>;
|
|
};
|
|
|
|
ETV570 {
|
|
clock-frequency = <25200000>;
|
|
hactive = <640>;
|
|
vactive = <480>;
|
|
hback-porch = <114>;
|
|
hsync-len = <30>;
|
|
hfront-porch = <16>;
|
|
vback-porch = <32>;
|
|
vsync-len = <3>;
|
|
vfront-porch = <10>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <1>;
|
|
};
|
|
|
|
ET0350 {
|
|
clock-frequency = <6413760>;
|
|
hactive = <320>;
|
|
vactive = <240>;
|
|
hback-porch = <34>;
|
|
hsync-len = <34>;
|
|
hfront-porch = <20>;
|
|
vback-porch = <15>;
|
|
vsync-len = <3>;
|
|
vfront-porch = <4>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <1>;
|
|
};
|
|
|
|
ET0430 {
|
|
clock-frequency = <9009000>;
|
|
hactive = <480>;
|
|
vactive = <272>;
|
|
hback-porch = <2>;
|
|
hsync-len = <41>;
|
|
hfront-porch = <2>;
|
|
vback-porch = <2>;
|
|
vsync-len = <10>;
|
|
vfront-porch = <2>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <0>;
|
|
};
|
|
|
|
ET0500 {
|
|
clock-frequency = <33264000>;
|
|
hactive = <800>;
|
|
vactive = <480>;
|
|
hback-porch = <88>;
|
|
hsync-len = <128>;
|
|
hfront-porch = <40>;
|
|
vback-porch = <33>;
|
|
vsync-len = <2>;
|
|
vfront-porch = <10>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <1>;
|
|
};
|
|
|
|
ET0700 { /* same as ET0500 */
|
|
clock-frequency = <33264000>;
|
|
hactive = <800>;
|
|
vactive = <480>;
|
|
hback-porch = <88>;
|
|
hsync-len = <128>;
|
|
hfront-porch = <40>;
|
|
vback-porch = <33>;
|
|
vsync-len = <2>;
|
|
vfront-porch = <10>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <1>;
|
|
};
|
|
|
|
ETQ570 {
|
|
clock-frequency = <6596040>;
|
|
hactive = <320>;
|
|
vactive = <240>;
|
|
hback-porch = <38>;
|
|
hsync-len = <30>;
|
|
hfront-porch = <30>;
|
|
vback-porch = <16>;
|
|
vsync-len = <3>;
|
|
vfront-porch = <4>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <1>;
|
|
pixelclk-active = <1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pwm5 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm5>;
|
|
#pwm-cells = <3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&sai2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sai2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
|
|
uart-has-rtscts;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
|
|
uart-has-rtscts;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart5 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
|
|
uart-has-rtscts;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg1 {
|
|
vbus-supply = <®_usbotg_vbus>;
|
|
dr_mode = "peripheral";
|
|
disable-over-current;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg2 {
|
|
vbus-supply = <®_usbh1_vbus>;
|
|
dr_mode = "host";
|
|
disable-over-current;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
|
|
bus-width = <4>;
|
|
no-1-8-v;
|
|
cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
|
|
fsl,wp-controller;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_hog>;
|
|
|
|
pinctrl_hog: hoggrp {
|
|
};
|
|
|
|
pinctrl_led: ledgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
|
|
>;
|
|
};
|
|
|
|
pinctrl_disp0_1: disp0grp-1 {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
|
|
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
|
|
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
|
|
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
|
|
/* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
|
|
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
|
|
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
|
|
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
|
|
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
|
|
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
|
|
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
|
|
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
|
|
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
|
|
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
|
|
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
|
|
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
|
|
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
|
|
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
|
|
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
|
|
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
|
|
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
|
|
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
|
|
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
|
|
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
|
|
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
|
|
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
|
|
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
|
|
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
|
|
>;
|
|
};
|
|
|
|
pinctrl_disp0_2: disp0grp-2 {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
|
|
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
|
|
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
|
|
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
|
|
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10
|
|
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
|
|
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
|
|
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
|
|
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
|
|
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
|
|
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
|
|
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
|
|
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
|
|
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
|
|
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
|
|
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
|
|
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
|
|
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
|
|
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
|
|
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
|
|
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
|
|
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
|
|
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
|
|
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
|
|
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
|
|
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
|
|
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
|
|
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
|
|
>;
|
|
};
|
|
|
|
pinctrl_ecspi2: ecspi2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
|
|
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
|
|
MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */
|
|
MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */
|
|
MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */
|
|
>;
|
|
};
|
|
|
|
pinctrl_edt_ft5x06: edt-ft5x06grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */
|
|
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */
|
|
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet1: enet1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
|
|
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
|
|
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0
|
|
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0
|
|
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0
|
|
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
|
|
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
|
|
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet2: enet2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
|
|
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
|
|
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0
|
|
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0
|
|
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0
|
|
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
|
|
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
|
|
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet1_mdio: enet1-mdiogrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0
|
|
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_etnphy_power: etnphy-pwrgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
|
|
>;
|
|
};
|
|
|
|
pinctrl_etnphy0_int: etnphy-intgrp-0 {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
|
|
>;
|
|
};
|
|
|
|
pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
|
|
>;
|
|
};
|
|
|
|
pinctrl_etnphy1_int: etnphy-intgrp-1 {
|
|
fsl,pins = <
|
|
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
|
|
>;
|
|
};
|
|
|
|
pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
|
|
fsl,pins = <
|
|
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
|
|
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
|
|
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
|
|
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
|
|
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
|
|
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
|
|
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
|
|
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
|
|
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c_gpio: i2c-gpiogrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */
|
|
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1
|
|
MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_kpp: kppgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcd_pwr: lcd-pwrgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcd_rst: lcd-rstgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm5: pwm5grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai2: sai2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */
|
|
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */
|
|
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */
|
|
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */
|
|
>;
|
|
};
|
|
|
|
pinctrl_spi_gpio: spi-gpiogrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
|
|
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
|
|
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */
|
|
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */
|
|
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */
|
|
>;
|
|
};
|
|
|
|
pinctrl_tsc2007: tsc2007grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0
|
|
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1_rtscts: uart1-rtsctsgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0
|
|
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0
|
|
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2_rtscts: uart2-rtsctsgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0
|
|
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0
|
|
MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5_rtscts: uart5-rtsctsgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0
|
|
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbh1_oc: usbh1-ocgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbh1_vbus: usbh1-vbusgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg_oc: usbotg-ocgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg_vbus: usbotg-vbusgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_cd: usdhc1cdgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1
|
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1
|
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1
|
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1
|
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1
|
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1
|
|
/* eMMC RESET */
|
|
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
|
|
>;
|
|
};
|
|
};
|