mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 15:04:27 +08:00
34d5003bfb
The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
||
|---|---|---|
| .. | ||
| clk-gate-a10.c | ||
| clk-gate.c | ||
| clk-periph-a10.c | ||
| clk-periph.c | ||
| clk-pll-a10.c | ||
| clk-pll.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||