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c5601e0720
This code was using -1 to represent that there was no reset function.
Unfortunately, the -1 was stored in u8 so the if (clks[i].rs_id >= 0)
condition was always true. This lead to an out of bounds access in
visconti_clk_register_gates().
Fixes: b4cbe606dc ("clk: visconti: Add support common clock driver and reset driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/20220316083533.GA30941@kili
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
292 lines
10 KiB
C
292 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Toshiba Visconti clock controller
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*
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* Copyright (c) 2021 TOSHIBA CORPORATION
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* Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/toshiba,tmpv770x.h>
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#include <dt-bindings/reset/toshiba,tmpv770x.h>
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#include "clkc.h"
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#include "reset.h"
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static DEFINE_SPINLOCK(tmpv770x_clk_lock);
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static DEFINE_SPINLOCK(tmpv770x_rst_lock);
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static const struct clk_parent_data clks_parent_data[] = {
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{ .fw_name = "pipll1", .name = "pipll1", },
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};
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static const struct clk_parent_data pietherplls_parent_data[] = {
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{ .fw_name = "pietherpll", .name = "pietherpll", },
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};
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static const struct visconti_fixed_clk fixed_clk_tables[] = {
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/* PLL1 */
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/* PICMPT0/1, PITSC, PIUWDT, PISWDT, PISBUS, PIPMU, PIGPMU, PITMU */
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/* PIEMM, PIMISC, PIGCOMM, PIDCOMM, PIMBUS, PIGPIO, PIPGM */
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{ TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
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/* PISBUS */
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{ TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
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/* PICOBUS_CLK */
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{ TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
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/* PIDNNPLL */
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/* CONN_CLK, PIMBUS, PICRC0/1 */
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{ TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
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{ TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
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{ TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
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};
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static const struct visconti_clk_gate_table pietherpll_clk_gate_tables[] = {
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/* pietherpll */
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{ TMPV770X_CLK_PIETHER_2P5M, "piether_2p5m",
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pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
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CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
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TMPV770X_RESET_PIETHER_2P5M, },
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{ TMPV770X_CLK_PIETHER_25M, "piether_25m",
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pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
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CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
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TMPV770X_RESET_PIETHER_25M, },
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{ TMPV770X_CLK_PIETHER_50M, "piether_50m",
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pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
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CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
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TMPV770X_RESET_PIETHER_50M, },
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{ TMPV770X_CLK_PIETHER_125M, "piether_125m",
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pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
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CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
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TMPV770X_RESET_PIETHER_125M, },
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};
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static const struct visconti_clk_gate_table clk_gate_tables[] = {
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{ TMPV770X_CLK_HOX, "hox",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x4c, 0x14c, 0, 1,
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TMPV770X_RESET_HOX, },
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{ TMPV770X_CLK_PCIE_MSTR, "pcie_mstr",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x38, 0x138, 0, 1,
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TMPV770X_RESET_PCIE_MSTR, },
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{ TMPV770X_CLK_PCIE_AUX, "pcie_aux",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x38, 0x138, 1, 24,
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TMPV770X_RESET_PCIE_AUX, },
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{ TMPV770X_CLK_PIINTC, "piintc",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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CLK_IGNORE_UNUSED, 0x8, 0x108, 0, 2, //FIX!!
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TMPV770X_RESET_PIINTC,},
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{ TMPV770X_CLK_PIETHER_BUS, "piether_bus",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x34, 0x134, 0, 2,
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TMPV770X_RESET_PIETHER_BUS, }, /* BUS_CLK */
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{ TMPV770X_CLK_PISPI0, "pispi0",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x28, 0x128, 0, 2,
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TMPV770X_RESET_PISPI0, },
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{ TMPV770X_CLK_PISPI1, "pispi1",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x28, 0x128, 1, 2,
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TMPV770X_RESET_PISPI1, },
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{ TMPV770X_CLK_PISPI2, "pispi2",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x28, 0x128, 2, 2,
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TMPV770X_RESET_PISPI2, },
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{ TMPV770X_CLK_PISPI3, "pispi3",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x28, 0x128, 3, 2,
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TMPV770X_RESET_PISPI3,},
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{ TMPV770X_CLK_PISPI4, "pispi4",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x28, 0x128, 4, 2,
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TMPV770X_RESET_PISPI4, },
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{ TMPV770X_CLK_PISPI5, "pispi5",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x28, 0x128, 5, 2,
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TMPV770X_RESET_PISPI5},
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{ TMPV770X_CLK_PISPI6, "pispi6",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x28, 0x128, 6, 2,
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TMPV770X_RESET_PISPI6,},
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{ TMPV770X_CLK_PIUART0, "piuart0",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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//CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2c, 0x12c, 0, 4,
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0, 0x2c, 0x12c, 0, 4,
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TMPV770X_RESET_PIUART0,},
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{ TMPV770X_CLK_PIUART1, "piuart1",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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//CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2c, 0x12c, 1, 4,
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0, 0x2c, 0x12c, 1, 4,
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TMPV770X_RESET_PIUART1, },
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{ TMPV770X_CLK_PIUART2, "piuart2",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x2c, 0x12c, 2, 4,
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TMPV770X_RESET_PIUART2, },
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{ TMPV770X_CLK_PIUART3, "piuart3",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x2c, 0x12c, 3, 4,
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TMPV770X_RESET_PIUART3, },
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{ TMPV770X_CLK_PII2C0, "pii2c0",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 0, 4,
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TMPV770X_RESET_PII2C0, },
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{ TMPV770X_CLK_PII2C1, "pii2c1",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 1, 4,
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TMPV770X_RESET_PII2C1, },
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{ TMPV770X_CLK_PII2C2, "pii2c2",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 2, 4,
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TMPV770X_RESET_PII2C2, },
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{ TMPV770X_CLK_PII2C3, "pii2c3",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 3, 4,
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TMPV770X_RESET_PII2C3,},
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{ TMPV770X_CLK_PII2C4, "pii2c4",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 4, 4,
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TMPV770X_RESET_PII2C4, },
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{ TMPV770X_CLK_PII2C5, "pii2c5",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 5, 4,
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TMPV770X_RESET_PII2C5, },
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{ TMPV770X_CLK_PII2C6, "pii2c6",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 6, 4,
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TMPV770X_RESET_PII2C6, },
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{ TMPV770X_CLK_PII2C7, "pii2c7",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 7, 4,
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TMPV770X_RESET_PII2C7, },
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{ TMPV770X_CLK_PII2C8, "pii2c8",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x30, 0x130, 8, 4,
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TMPV770X_RESET_PII2C8, },
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/* PIPCMIF */
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{ TMPV770X_CLK_PIPCMIF, "pipcmif",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x64, 0x164, 0, 4,
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TMPV770X_RESET_PIPCMIF, },
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/* PISYSTEM */
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{ TMPV770X_CLK_WRCK, "wrck",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x68, 0x168, 9, 32,
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NO_RESET, },
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{ TMPV770X_CLK_PICKMON, "pickmon",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x10, 0x110, 8, 4,
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TMPV770X_RESET_PICKMON, },
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{ TMPV770X_CLK_SBUSCLK, "sbusclk",
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clks_parent_data, ARRAY_SIZE(clks_parent_data),
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0, 0x14, 0x114, 0, 4,
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TMPV770X_RESET_SBUSCLK, },
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};
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static const struct visconti_reset_data clk_reset_data[] = {
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[TMPV770X_RESET_PIETHER_2P5M] = { 0x434, 0x534, 4, },
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[TMPV770X_RESET_PIETHER_25M] = { 0x434, 0x534, 5, },
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[TMPV770X_RESET_PIETHER_50M] = { 0x434, 0x534, 6, },
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[TMPV770X_RESET_PIETHER_125M] = { 0x434, 0x534, 7, },
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[TMPV770X_RESET_HOX] = { 0x44c, 0x54c, 0, },
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[TMPV770X_RESET_PCIE_MSTR] = { 0x438, 0x538, 0, },
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[TMPV770X_RESET_PCIE_AUX] = { 0x438, 0x538, 1, },
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[TMPV770X_RESET_PIINTC] = { 0x408, 0x508, 0, },
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[TMPV770X_RESET_PIETHER_BUS] = { 0x434, 0x534, 0, },
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[TMPV770X_RESET_PISPI0] = { 0x428, 0x528, 0, },
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[TMPV770X_RESET_PISPI1] = { 0x428, 0x528, 1, },
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[TMPV770X_RESET_PISPI2] = { 0x428, 0x528, 2, },
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[TMPV770X_RESET_PISPI3] = { 0x428, 0x528, 3, },
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[TMPV770X_RESET_PISPI4] = { 0x428, 0x528, 4, },
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[TMPV770X_RESET_PISPI5] = { 0x428, 0x528, 5, },
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[TMPV770X_RESET_PISPI6] = { 0x428, 0x528, 6, },
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[TMPV770X_RESET_PIUART0] = { 0x42c, 0x52c, 0, },
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[TMPV770X_RESET_PIUART1] = { 0x42c, 0x52c, 1, },
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[TMPV770X_RESET_PIUART2] = { 0x42c, 0x52c, 2, },
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[TMPV770X_RESET_PIUART3] = { 0x42c, 0x52c, 3, },
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[TMPV770X_RESET_PII2C0] = { 0x430, 0x530, 0, },
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[TMPV770X_RESET_PII2C1] = { 0x430, 0x530, 1, },
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[TMPV770X_RESET_PII2C2] = { 0x430, 0x530, 2, },
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[TMPV770X_RESET_PII2C3] = { 0x430, 0x530, 3, },
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[TMPV770X_RESET_PII2C4] = { 0x430, 0x530, 4, },
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[TMPV770X_RESET_PII2C5] = { 0x430, 0x530, 5, },
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[TMPV770X_RESET_PII2C6] = { 0x430, 0x530, 6, },
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[TMPV770X_RESET_PII2C7] = { 0x430, 0x530, 7, },
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[TMPV770X_RESET_PII2C8] = { 0x430, 0x530, 8, },
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[TMPV770X_RESET_PIPCMIF] = { 0x464, 0x564, 0, },
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[TMPV770X_RESET_PICKMON] = { 0x410, 0x510, 8, },
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[TMPV770X_RESET_SBUSCLK] = { 0x414, 0x514, 0, },
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};
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static int visconti_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct visconti_clk_provider *ctx;
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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int ret, i;
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regmap = syscon_node_to_regmap(np);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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ctx = visconti_init_clk(dev, regmap, TMPV770X_NR_CLK);
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if (IS_ERR(ctx))
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return PTR_ERR(ctx);
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ret = visconti_register_reset_controller(dev, regmap, clk_reset_data,
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TMPV770X_NR_RESET,
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&visconti_reset_ops,
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&tmpv770x_rst_lock);
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if (ret) {
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dev_err(dev, "Failed to register reset controller: %d\n", ret);
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return ret;
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}
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for (i = 0; i < (ARRAY_SIZE(fixed_clk_tables)); i++)
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ctx->clk_data.hws[fixed_clk_tables[i].id] =
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clk_hw_register_fixed_factor(NULL,
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fixed_clk_tables[i].name,
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fixed_clk_tables[i].parent,
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fixed_clk_tables[i].flag,
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fixed_clk_tables[i].mult,
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fixed_clk_tables[i].div);
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ret = visconti_clk_register_gates(ctx, clk_gate_tables,
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ARRAY_SIZE(clk_gate_tables), clk_reset_data,
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&tmpv770x_clk_lock);
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if (ret) {
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dev_err(dev, "Failed to register main clock gate: %d\n", ret);
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return ret;
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}
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ret = visconti_clk_register_gates(ctx, pietherpll_clk_gate_tables,
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ARRAY_SIZE(pietherpll_clk_gate_tables),
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clk_reset_data, &tmpv770x_clk_lock);
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if (ret) {
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dev_err(dev, "Failed to register pietherpll clock gate: %d\n", ret);
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return ret;
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}
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return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &ctx->clk_data);
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}
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static const struct of_device_id visconti_clk_ids[] = {
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{ .compatible = "toshiba,tmpv7708-pismu", },
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{ }
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};
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static struct platform_driver visconti_clk_driver = {
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.probe = visconti_clk_probe,
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.driver = {
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.name = "visconti-clk",
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.of_match_table = visconti_clk_ids,
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},
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};
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builtin_platform_driver(visconti_clk_driver);
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