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0bb7e560f8
If 'mmc_of_parse()' fails, we must undo the previous 'dma_request_chan()' call. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20201208203527.49262-1-christophe.jaillet@wanadoo.fr Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
725 lines
18 KiB
C
725 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Portions copyright (C) 2003 Russell King, PXA MMCI Driver
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* Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
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*
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* Copyright 2008 Embedded Alley Solutions, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/dma/mxs-dma.h>
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#include <linux/highmem.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/completion.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/regulator/consumer.h>
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#include <linux/module.h>
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#include <linux/stmp_device.h>
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#include <linux/spi/mxs-spi.h>
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#define DRIVER_NAME "mxs-mmc"
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#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
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BM_SSP_CTRL1_RESP_ERR_IRQ | \
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BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
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BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
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BM_SSP_CTRL1_DATA_CRC_IRQ | \
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BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
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BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
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BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
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/* card detect polling timeout */
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#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
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struct mxs_mmc_host {
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struct mxs_ssp ssp;
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struct mmc_host *mmc;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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unsigned char bus_width;
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spinlock_t lock;
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int sdio_irq_en;
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bool broken_cd;
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};
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static int mxs_mmc_get_cd(struct mmc_host *mmc)
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{
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struct mxs_mmc_host *host = mmc_priv(mmc);
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struct mxs_ssp *ssp = &host->ssp;
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int present, ret;
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if (host->broken_cd)
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return -ENOSYS;
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ret = mmc_gpio_get_cd(mmc);
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if (ret >= 0)
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return ret;
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present = mmc->caps & MMC_CAP_NEEDS_POLL ||
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!(readl(ssp->base + HW_SSP_STATUS(ssp)) &
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BM_SSP_STATUS_CARD_DETECT);
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if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
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present = !present;
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return present;
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}
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static int mxs_mmc_reset(struct mxs_mmc_host *host)
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{
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struct mxs_ssp *ssp = &host->ssp;
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u32 ctrl0, ctrl1;
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int ret;
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ret = stmp_reset_block(ssp->base);
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if (ret)
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return ret;
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ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
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ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
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BF_SSP(0x7, CTRL1_WORD_LENGTH) |
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BM_SSP_CTRL1_DMA_ENABLE |
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BM_SSP_CTRL1_POLARITY |
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BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
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BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
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BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
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BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
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BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
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writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
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BF_SSP(2, TIMING_CLOCK_DIVIDE) |
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BF_SSP(0, TIMING_CLOCK_RATE),
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ssp->base + HW_SSP_TIMING(ssp));
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if (host->sdio_irq_en) {
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ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
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ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
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}
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writel(ctrl0, ssp->base + HW_SSP_CTRL0);
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writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
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return 0;
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}
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static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
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struct mmc_command *cmd);
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static void mxs_mmc_request_done(struct mxs_mmc_host *host)
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{
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struct mmc_command *cmd = host->cmd;
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struct mmc_data *data = host->data;
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struct mmc_request *mrq = host->mrq;
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struct mxs_ssp *ssp = &host->ssp;
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if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
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if (mmc_resp_type(cmd) & MMC_RSP_136) {
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cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
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cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
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cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
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cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
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} else {
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cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
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}
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}
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if (cmd == mrq->sbc) {
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/* Finished CMD23, now send actual command. */
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mxs_mmc_start_cmd(host, mrq->cmd);
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return;
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} else if (data) {
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dma_unmap_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, ssp->dma_dir);
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/*
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* If there was an error on any block, we mark all
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* data blocks as being in error.
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*/
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if (!data->error)
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data->bytes_xfered = data->blocks * data->blksz;
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else
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data->bytes_xfered = 0;
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host->data = NULL;
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if (data->stop && (data->error || !mrq->sbc)) {
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mxs_mmc_start_cmd(host, mrq->stop);
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return;
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}
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}
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host->mrq = NULL;
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mmc_request_done(host->mmc, mrq);
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}
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static void mxs_mmc_dma_irq_callback(void *param)
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{
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struct mxs_mmc_host *host = param;
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mxs_mmc_request_done(host);
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}
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static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
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{
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struct mxs_mmc_host *host = dev_id;
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struct mmc_command *cmd = host->cmd;
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struct mmc_data *data = host->data;
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struct mxs_ssp *ssp = &host->ssp;
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u32 stat;
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spin_lock(&host->lock);
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stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
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writel(stat & MXS_MMC_IRQ_BITS,
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ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
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spin_unlock(&host->lock);
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if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
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mmc_signal_sdio_irq(host->mmc);
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if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
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cmd->error = -ETIMEDOUT;
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else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
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cmd->error = -EIO;
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if (data) {
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if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
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BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
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data->error = -ETIMEDOUT;
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else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
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data->error = -EILSEQ;
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else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
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BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
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data->error = -EIO;
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}
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return IRQ_HANDLED;
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}
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static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
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struct mxs_mmc_host *host, unsigned long flags)
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{
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struct mxs_ssp *ssp = &host->ssp;
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struct dma_async_tx_descriptor *desc;
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struct mmc_data *data = host->data;
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struct scatterlist * sgl;
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unsigned int sg_len;
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if (data) {
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/* data */
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dma_map_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, ssp->dma_dir);
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sgl = data->sg;
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sg_len = data->sg_len;
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} else {
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/* pio */
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sgl = (struct scatterlist *) ssp->ssp_pio_words;
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sg_len = SSP_PIO_NUM;
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}
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desc = dmaengine_prep_slave_sg(ssp->dmach,
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sgl, sg_len, ssp->slave_dirn, flags);
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if (desc) {
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desc->callback = mxs_mmc_dma_irq_callback;
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desc->callback_param = host;
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} else {
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if (data)
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dma_unmap_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, ssp->dma_dir);
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}
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return desc;
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}
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static void mxs_mmc_bc(struct mxs_mmc_host *host)
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{
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struct mxs_ssp *ssp = &host->ssp;
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struct mmc_command *cmd = host->cmd;
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struct dma_async_tx_descriptor *desc;
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u32 ctrl0, cmd0, cmd1;
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ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
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cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
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cmd1 = cmd->arg;
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if (host->sdio_irq_en) {
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ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
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cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
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}
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ssp->ssp_pio_words[0] = ctrl0;
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ssp->ssp_pio_words[1] = cmd0;
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ssp->ssp_pio_words[2] = cmd1;
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ssp->dma_dir = DMA_NONE;
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ssp->slave_dirn = DMA_TRANS_NONE;
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desc = mxs_mmc_prep_dma(host, MXS_DMA_CTRL_WAIT4END);
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if (!desc)
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goto out;
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dmaengine_submit(desc);
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dma_async_issue_pending(ssp->dmach);
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return;
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out:
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dev_warn(mmc_dev(host->mmc),
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"%s: failed to prep dma\n", __func__);
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}
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static void mxs_mmc_ac(struct mxs_mmc_host *host)
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{
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struct mxs_ssp *ssp = &host->ssp;
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struct mmc_command *cmd = host->cmd;
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struct dma_async_tx_descriptor *desc;
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u32 ignore_crc, get_resp, long_resp;
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u32 ctrl0, cmd0, cmd1;
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ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
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0 : BM_SSP_CTRL0_IGNORE_CRC;
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get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
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BM_SSP_CTRL0_GET_RESP : 0;
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long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
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BM_SSP_CTRL0_LONG_RESP : 0;
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ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
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cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
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cmd1 = cmd->arg;
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if (cmd->opcode == MMC_STOP_TRANSMISSION)
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cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
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if (host->sdio_irq_en) {
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ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
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cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
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}
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ssp->ssp_pio_words[0] = ctrl0;
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ssp->ssp_pio_words[1] = cmd0;
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ssp->ssp_pio_words[2] = cmd1;
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ssp->dma_dir = DMA_NONE;
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ssp->slave_dirn = DMA_TRANS_NONE;
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desc = mxs_mmc_prep_dma(host, MXS_DMA_CTRL_WAIT4END);
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if (!desc)
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goto out;
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dmaengine_submit(desc);
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dma_async_issue_pending(ssp->dmach);
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return;
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out:
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dev_warn(mmc_dev(host->mmc),
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"%s: failed to prep dma\n", __func__);
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}
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static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
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{
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const unsigned int ssp_timeout_mul = 4096;
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/*
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* Calculate ticks in ms since ns are large numbers
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* and might overflow
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*/
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const unsigned int clock_per_ms = clock_rate / 1000;
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const unsigned int ms = ns / 1000;
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const unsigned int ticks = ms * clock_per_ms;
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const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
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WARN_ON(ssp_ticks == 0);
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return ssp_ticks;
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}
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static void mxs_mmc_adtc(struct mxs_mmc_host *host)
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{
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struct mmc_command *cmd = host->cmd;
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struct mmc_data *data = cmd->data;
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struct dma_async_tx_descriptor *desc;
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struct scatterlist *sgl = data->sg, *sg;
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unsigned int sg_len = data->sg_len;
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unsigned int i;
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unsigned short dma_data_dir, timeout;
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enum dma_transfer_direction slave_dirn;
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unsigned int data_size = 0, log2_blksz;
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unsigned int blocks = data->blocks;
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struct mxs_ssp *ssp = &host->ssp;
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u32 ignore_crc, get_resp, long_resp, read;
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u32 ctrl0, cmd0, cmd1, val;
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ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
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0 : BM_SSP_CTRL0_IGNORE_CRC;
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get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
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BM_SSP_CTRL0_GET_RESP : 0;
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long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
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BM_SSP_CTRL0_LONG_RESP : 0;
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if (data->flags & MMC_DATA_WRITE) {
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dma_data_dir = DMA_TO_DEVICE;
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slave_dirn = DMA_MEM_TO_DEV;
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read = 0;
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} else {
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dma_data_dir = DMA_FROM_DEVICE;
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slave_dirn = DMA_DEV_TO_MEM;
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read = BM_SSP_CTRL0_READ;
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}
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ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
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ignore_crc | get_resp | long_resp |
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BM_SSP_CTRL0_DATA_XFER | read |
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BM_SSP_CTRL0_WAIT_FOR_IRQ |
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BM_SSP_CTRL0_ENABLE;
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cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
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/* get logarithm to base 2 of block size for setting register */
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log2_blksz = ilog2(data->blksz);
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/*
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* take special care of the case that data size from data->sg
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* is not equal to blocks x blksz
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*/
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for_each_sg(sgl, sg, sg_len, i)
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data_size += sg->length;
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if (data_size != data->blocks * data->blksz)
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blocks = 1;
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/* xfer count, block size and count need to be set differently */
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if (ssp_is_old(ssp)) {
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ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
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cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
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BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
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} else {
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writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
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writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
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BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
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ssp->base + HW_SSP_BLOCK_SIZE);
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}
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if (cmd->opcode == SD_IO_RW_EXTENDED)
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cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
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cmd1 = cmd->arg;
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if (host->sdio_irq_en) {
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ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
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cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
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}
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/* set the timeout count */
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timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
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val = readl(ssp->base + HW_SSP_TIMING(ssp));
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val &= ~(BM_SSP_TIMING_TIMEOUT);
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val |= BF_SSP(timeout, TIMING_TIMEOUT);
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writel(val, ssp->base + HW_SSP_TIMING(ssp));
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/* pio */
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ssp->ssp_pio_words[0] = ctrl0;
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ssp->ssp_pio_words[1] = cmd0;
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ssp->ssp_pio_words[2] = cmd1;
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ssp->dma_dir = DMA_NONE;
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ssp->slave_dirn = DMA_TRANS_NONE;
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desc = mxs_mmc_prep_dma(host, 0);
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if (!desc)
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goto out;
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/* append data sg */
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WARN_ON(host->data != NULL);
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host->data = data;
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ssp->dma_dir = dma_data_dir;
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ssp->slave_dirn = slave_dirn;
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desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | MXS_DMA_CTRL_WAIT4END);
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if (!desc)
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goto out;
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dmaengine_submit(desc);
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dma_async_issue_pending(ssp->dmach);
|
|
return;
|
|
out:
|
|
dev_warn(mmc_dev(host->mmc),
|
|
"%s: failed to prep dma\n", __func__);
|
|
}
|
|
|
|
static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
|
|
struct mmc_command *cmd)
|
|
{
|
|
host->cmd = cmd;
|
|
|
|
switch (mmc_cmd_type(cmd)) {
|
|
case MMC_CMD_BC:
|
|
mxs_mmc_bc(host);
|
|
break;
|
|
case MMC_CMD_BCR:
|
|
mxs_mmc_ac(host);
|
|
break;
|
|
case MMC_CMD_AC:
|
|
mxs_mmc_ac(host);
|
|
break;
|
|
case MMC_CMD_ADTC:
|
|
mxs_mmc_adtc(host);
|
|
break;
|
|
default:
|
|
dev_warn(mmc_dev(host->mmc),
|
|
"%s: unknown MMC command\n", __func__);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
|
|
WARN_ON(host->mrq != NULL);
|
|
host->mrq = mrq;
|
|
|
|
if (mrq->sbc)
|
|
mxs_mmc_start_cmd(host, mrq->sbc);
|
|
else
|
|
mxs_mmc_start_cmd(host, mrq->cmd);
|
|
}
|
|
|
|
static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_8)
|
|
host->bus_width = 2;
|
|
else if (ios->bus_width == MMC_BUS_WIDTH_4)
|
|
host->bus_width = 1;
|
|
else
|
|
host->bus_width = 0;
|
|
|
|
if (ios->clock)
|
|
mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
|
|
}
|
|
|
|
static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
|
{
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
struct mxs_ssp *ssp = &host->ssp;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
host->sdio_irq_en = enable;
|
|
|
|
if (enable) {
|
|
writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
|
writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
|
|
ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
|
|
} else {
|
|
writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
|
writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
|
|
ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) &
|
|
BM_SSP_STATUS_SDIO_IRQ)
|
|
mmc_signal_sdio_irq(host->mmc);
|
|
|
|
}
|
|
|
|
static const struct mmc_host_ops mxs_mmc_ops = {
|
|
.request = mxs_mmc_request,
|
|
.get_ro = mmc_gpio_get_ro,
|
|
.get_cd = mxs_mmc_get_cd,
|
|
.set_ios = mxs_mmc_set_ios,
|
|
.enable_sdio_irq = mxs_mmc_enable_sdio_irq,
|
|
};
|
|
|
|
static const struct of_device_id mxs_mmc_dt_ids[] = {
|
|
{ .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, },
|
|
{ .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
|
|
|
|
static int mxs_mmc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct mxs_mmc_host *host;
|
|
struct mmc_host *mmc;
|
|
int ret = 0, irq_err;
|
|
struct regulator *reg_vmmc;
|
|
struct mxs_ssp *ssp;
|
|
|
|
irq_err = platform_get_irq(pdev, 0);
|
|
if (irq_err < 0)
|
|
return irq_err;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
|
|
if (!mmc)
|
|
return -ENOMEM;
|
|
|
|
host = mmc_priv(mmc);
|
|
ssp = &host->ssp;
|
|
ssp->dev = &pdev->dev;
|
|
ssp->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(ssp->base)) {
|
|
ret = PTR_ERR(ssp->base);
|
|
goto out_mmc_free;
|
|
}
|
|
|
|
ssp->devid = (enum mxs_ssp_id)of_device_get_match_data(&pdev->dev);
|
|
|
|
host->mmc = mmc;
|
|
host->sdio_irq_en = 0;
|
|
|
|
reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
|
|
if (!IS_ERR(reg_vmmc)) {
|
|
ret = regulator_enable(reg_vmmc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev,
|
|
"Failed to enable vmmc regulator: %d\n", ret);
|
|
goto out_mmc_free;
|
|
}
|
|
}
|
|
|
|
ssp->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(ssp->clk)) {
|
|
ret = PTR_ERR(ssp->clk);
|
|
goto out_mmc_free;
|
|
}
|
|
ret = clk_prepare_enable(ssp->clk);
|
|
if (ret)
|
|
goto out_mmc_free;
|
|
|
|
ret = mxs_mmc_reset(host);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to reset mmc: %d\n", ret);
|
|
goto out_clk_disable;
|
|
}
|
|
|
|
ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
|
|
if (IS_ERR(ssp->dmach)) {
|
|
dev_err(mmc_dev(host->mmc),
|
|
"%s: failed to request dma\n", __func__);
|
|
ret = PTR_ERR(ssp->dmach);
|
|
goto out_clk_disable;
|
|
}
|
|
|
|
/* set mmc core parameters */
|
|
mmc->ops = &mxs_mmc_ops;
|
|
mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
|
|
MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL | MMC_CAP_CMD23;
|
|
|
|
host->broken_cd = of_property_read_bool(np, "broken-cd");
|
|
|
|
mmc->f_min = 400000;
|
|
mmc->f_max = 288000000;
|
|
|
|
ret = mmc_of_parse(mmc);
|
|
if (ret)
|
|
goto out_free_dma;
|
|
|
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
mmc->max_segs = 52;
|
|
mmc->max_blk_size = 1 << 0xf;
|
|
mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
|
|
mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
|
|
mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
|
|
|
|
platform_set_drvdata(pdev, mmc);
|
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
|
|
dev_name(&pdev->dev), host);
|
|
if (ret)
|
|
goto out_free_dma;
|
|
|
|
ret = mmc_add_host(mmc);
|
|
if (ret)
|
|
goto out_free_dma;
|
|
|
|
dev_info(mmc_dev(host->mmc), "initialized\n");
|
|
|
|
return 0;
|
|
|
|
out_free_dma:
|
|
dma_release_channel(ssp->dmach);
|
|
out_clk_disable:
|
|
clk_disable_unprepare(ssp->clk);
|
|
out_mmc_free:
|
|
mmc_free_host(mmc);
|
|
return ret;
|
|
}
|
|
|
|
static int mxs_mmc_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
struct mxs_ssp *ssp = &host->ssp;
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
if (ssp->dmach)
|
|
dma_release_channel(ssp->dmach);
|
|
|
|
clk_disable_unprepare(ssp->clk);
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int mxs_mmc_suspend(struct device *dev)
|
|
{
|
|
struct mmc_host *mmc = dev_get_drvdata(dev);
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
struct mxs_ssp *ssp = &host->ssp;
|
|
|
|
clk_disable_unprepare(ssp->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int mxs_mmc_resume(struct device *dev)
|
|
{
|
|
struct mmc_host *mmc = dev_get_drvdata(dev);
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
struct mxs_ssp *ssp = &host->ssp;
|
|
|
|
return clk_prepare_enable(ssp->clk);
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(mxs_mmc_pm_ops, mxs_mmc_suspend, mxs_mmc_resume);
|
|
|
|
static struct platform_driver mxs_mmc_driver = {
|
|
.probe = mxs_mmc_probe,
|
|
.remove = mxs_mmc_remove,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.pm = &mxs_mmc_pm_ops,
|
|
.of_match_table = mxs_mmc_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mxs_mmc_driver);
|
|
|
|
MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
|
|
MODULE_AUTHOR("Freescale Semiconductor");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|