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228fe71379
Use lock guards from cleanup.h to simplify locking. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
588 lines
13 KiB
C
588 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Tangier pinctrl driver
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*
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* Copyright (C) 2016, 2023 Intel Corporation
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*
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* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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* Raag Jadav <raag.jadav@intel.com>
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*/
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/overflow.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include "../core.h"
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#include "pinctrl-intel.h"
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#include "pinctrl-tangier.h"
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#define SLEW_OFFSET 0x000
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#define BUFCFG_OFFSET 0x100
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#define MISC_OFFSET 0x300
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#define BUFCFG_PINMODE_SHIFT 0
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#define BUFCFG_PINMODE_MASK GENMASK(2, 0)
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#define BUFCFG_PINMODE_GPIO 0
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#define BUFCFG_PUPD_VAL_SHIFT 4
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#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
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#define BUFCFG_PUPD_VAL_2K 0
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#define BUFCFG_PUPD_VAL_20K 1
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#define BUFCFG_PUPD_VAL_50K 2
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#define BUFCFG_PUPD_VAL_910 3
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#define BUFCFG_PU_EN BIT(8)
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#define BUFCFG_PD_EN BIT(9)
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#define BUFCFG_Px_EN_MASK GENMASK(9, 8)
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#define BUFCFG_SLEWSEL BIT(10)
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#define BUFCFG_OVINEN BIT(12)
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#define BUFCFG_OVINEN_EN BIT(13)
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#define BUFCFG_OVINEN_MASK GENMASK(13, 12)
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#define BUFCFG_OVOUTEN BIT(14)
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#define BUFCFG_OVOUTEN_EN BIT(15)
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#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
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#define BUFCFG_INDATAOV_VAL BIT(16)
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#define BUFCFG_INDATAOV_EN BIT(17)
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#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
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#define BUFCFG_OUTDATAOV_VAL BIT(18)
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#define BUFCFG_OUTDATAOV_EN BIT(19)
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#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
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#define BUFCFG_OD_EN BIT(21)
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#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
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static const struct tng_family *tng_get_family(struct tng_pinctrl *tp,
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unsigned int pin)
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{
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const struct tng_family *family;
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unsigned int i;
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for (i = 0; i < tp->nfamilies; i++) {
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family = &tp->families[i];
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if (pin >= family->pin_base &&
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pin < family->pin_base + family->npins)
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return family;
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}
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dev_warn(tp->dev, "failed to find family for pin %u\n", pin);
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return NULL;
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}
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static bool tng_buf_available(struct tng_pinctrl *tp, unsigned int pin)
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{
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const struct tng_family *family;
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family = tng_get_family(tp, pin);
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if (!family)
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return false;
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return !family->protected;
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}
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static void __iomem *tng_get_bufcfg(struct tng_pinctrl *tp, unsigned int pin)
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{
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const struct tng_family *family;
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unsigned int bufno;
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family = tng_get_family(tp, pin);
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if (!family)
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return NULL;
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bufno = pin_to_bufno(family, pin);
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return family->regs + BUFCFG_OFFSET + bufno * 4;
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}
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static int tng_read_bufcfg(struct tng_pinctrl *tp, unsigned int pin, u32 *value)
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{
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void __iomem *bufcfg;
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if (!tng_buf_available(tp, pin))
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return -EBUSY;
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bufcfg = tng_get_bufcfg(tp, pin);
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*value = readl(bufcfg);
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return 0;
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}
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static void tng_update_bufcfg(struct tng_pinctrl *tp, unsigned int pin,
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u32 bits, u32 mask)
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{
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void __iomem *bufcfg;
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u32 value;
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bufcfg = tng_get_bufcfg(tp, pin);
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value = readl(bufcfg);
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value = (value & ~mask) | (bits & mask);
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writel(value, bufcfg);
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}
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static int tng_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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return tp->ngroups;
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}
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static const char *tng_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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return tp->groups[group].grp.name;
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}
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static int tng_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
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const unsigned int **pins, unsigned int *npins)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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*pins = tp->groups[group].grp.pins;
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*npins = tp->groups[group].grp.npins;
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return 0;
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}
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static void tng_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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unsigned int pin)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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u32 value, mode;
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int ret;
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ret = tng_read_bufcfg(tp, pin, &value);
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if (ret) {
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seq_puts(s, "not available");
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return;
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}
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mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
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if (mode == BUFCFG_PINMODE_GPIO)
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seq_puts(s, "GPIO ");
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else
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seq_printf(s, "mode %d ", mode);
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seq_printf(s, "0x%08x", value);
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}
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static const struct pinctrl_ops tng_pinctrl_ops = {
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.get_groups_count = tng_get_groups_count,
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.get_group_name = tng_get_group_name,
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.get_group_pins = tng_get_group_pins,
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.pin_dbg_show = tng_pin_dbg_show,
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};
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static int tng_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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return tp->nfunctions;
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}
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static const char *tng_get_function_name(struct pinctrl_dev *pctldev,
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unsigned int function)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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return tp->functions[function].func.name;
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}
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static int tng_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned int function,
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const char * const **groups,
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unsigned int * const ngroups)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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*groups = tp->functions[function].func.groups;
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*ngroups = tp->functions[function].func.ngroups;
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return 0;
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}
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static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int function,
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unsigned int group)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pingroup *grp = &tp->groups[group];
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u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
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u32 mask = BUFCFG_PINMODE_MASK;
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unsigned int i;
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/*
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* All pins in the groups needs to be accessible and writable
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* before we can enable the mux for this group.
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*/
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for (i = 0; i < grp->grp.npins; i++) {
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if (!tng_buf_available(tp, grp->grp.pins[i]))
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return -EBUSY;
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}
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guard(raw_spinlock_irqsave)(&tp->lock);
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/* Now enable the mux setting for each pin in the group */
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for (i = 0; i < grp->grp.npins; i++)
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tng_update_bufcfg(tp, grp->grp.pins[i], bits, mask);
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return 0;
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}
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static int tng_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
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u32 mask = BUFCFG_PINMODE_MASK;
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if (!tng_buf_available(tp, pin))
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return -EBUSY;
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guard(raw_spinlock_irqsave)(&tp->lock);
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tng_update_bufcfg(tp, pin, bits, mask);
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return 0;
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}
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static const struct pinmux_ops tng_pinmux_ops = {
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.get_functions_count = tng_get_functions_count,
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.get_function_name = tng_get_function_name,
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.get_function_groups = tng_get_function_groups,
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.set_mux = tng_pinmux_set_mux,
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.gpio_request_enable = tng_gpio_request_enable,
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};
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static int tng_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *config)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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u32 value, term;
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u16 arg = 0;
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int ret;
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ret = tng_read_bufcfg(tp, pin, &value);
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if (ret)
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return -ENOTSUPP;
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term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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if (value & BUFCFG_Px_EN_MASK)
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return -EINVAL;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
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return -EINVAL;
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switch (term) {
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case BUFCFG_PUPD_VAL_910:
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arg = 910;
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break;
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case BUFCFG_PUPD_VAL_2K:
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arg = 2000;
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break;
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case BUFCFG_PUPD_VAL_20K:
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arg = 20000;
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break;
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case BUFCFG_PUPD_VAL_50K:
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arg = 50000;
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break;
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}
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
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return -EINVAL;
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switch (term) {
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case BUFCFG_PUPD_VAL_910:
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arg = 910;
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break;
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case BUFCFG_PUPD_VAL_2K:
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arg = 2000;
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break;
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case BUFCFG_PUPD_VAL_20K:
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arg = 20000;
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break;
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case BUFCFG_PUPD_VAL_50K:
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arg = 50000;
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break;
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}
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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if (value & BUFCFG_OD_EN)
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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if (!(value & BUFCFG_OD_EN))
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return -EINVAL;
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break;
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case PIN_CONFIG_SLEW_RATE:
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if (value & BUFCFG_SLEWSEL)
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arg = 1;
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
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unsigned long config)
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{
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unsigned int param = pinconf_to_config_param(config);
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unsigned int arg = pinconf_to_config_argument(config);
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u32 mask, term, value = 0;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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switch (arg) {
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case 50000:
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term = BUFCFG_PUPD_VAL_50K;
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break;
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case 1: /* Set default strength value in case none is given */
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case 20000:
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term = BUFCFG_PUPD_VAL_20K;
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break;
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case 2000:
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term = BUFCFG_PUPD_VAL_2K;
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break;
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case 910:
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term = BUFCFG_PUPD_VAL_910;
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break;
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default:
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return -EINVAL;
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}
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mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
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value = BUFCFG_PU_EN | (term << BUFCFG_PUPD_VAL_SHIFT);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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switch (arg) {
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case 50000:
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term = BUFCFG_PUPD_VAL_50K;
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break;
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case 1: /* Set default strength value in case none is given */
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case 20000:
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term = BUFCFG_PUPD_VAL_20K;
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break;
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case 2000:
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term = BUFCFG_PUPD_VAL_2K;
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break;
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case 910:
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term = BUFCFG_PUPD_VAL_910;
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break;
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default:
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return -EINVAL;
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}
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mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
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value = BUFCFG_PD_EN | (term << BUFCFG_PUPD_VAL_SHIFT);
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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mask = BUFCFG_OD_EN;
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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mask = BUFCFG_OD_EN;
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value = BUFCFG_OD_EN;
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break;
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case PIN_CONFIG_SLEW_RATE:
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mask = BUFCFG_SLEWSEL;
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if (arg)
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value = BUFCFG_SLEWSEL;
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break;
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default:
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return -EINVAL;
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}
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guard(raw_spinlock_irqsave)(&tp->lock);
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tng_update_bufcfg(tp, pin, value, mask);
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return 0;
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}
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static int tng_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int nconfigs)
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{
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struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
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unsigned int i;
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int ret;
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if (!tng_buf_available(tp, pin))
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return -ENOTSUPP;
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for (i = 0; i < nconfigs; i++) {
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switch (pinconf_to_config_param(configs[i])) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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case PIN_CONFIG_SLEW_RATE:
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ret = tng_config_set_pin(tp, pin, configs[i]);
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if (ret)
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return ret;
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break;
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default:
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return -ENOTSUPP;
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}
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}
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return 0;
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}
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static int tng_config_group_get(struct pinctrl_dev *pctldev,
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unsigned int group, unsigned long *config)
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{
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const unsigned int *pins;
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unsigned int npins;
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int ret;
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ret = tng_get_group_pins(pctldev, group, &pins, &npins);
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if (ret)
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return ret;
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return tng_config_get(pctldev, pins[0], config);
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}
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static int tng_config_group_set(struct pinctrl_dev *pctldev,
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unsigned int group, unsigned long *configs,
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unsigned int num_configs)
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{
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const unsigned int *pins;
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unsigned int npins;
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int i, ret;
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ret = tng_get_group_pins(pctldev, group, &pins, &npins);
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if (ret)
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return ret;
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for (i = 0; i < npins; i++) {
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ret = tng_config_set(pctldev, pins[i], configs, num_configs);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct pinconf_ops tng_pinconf_ops = {
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.is_generic = true,
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.pin_config_get = tng_config_get,
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.pin_config_set = tng_config_set,
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.pin_config_group_get = tng_config_group_get,
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.pin_config_group_set = tng_config_group_set,
|
|
};
|
|
|
|
static const struct pinctrl_desc tng_pinctrl_desc = {
|
|
.pctlops = &tng_pinctrl_ops,
|
|
.pmxops = &tng_pinmux_ops,
|
|
.confops = &tng_pinconf_ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int tng_pinctrl_probe(struct platform_device *pdev,
|
|
const struct tng_pinctrl *data)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct tng_family *families;
|
|
struct tng_pinctrl *tp;
|
|
size_t families_len;
|
|
void __iomem *regs;
|
|
unsigned int i;
|
|
|
|
tp = devm_kmemdup(dev, data, sizeof(*data), GFP_KERNEL);
|
|
if (!tp)
|
|
return -ENOMEM;
|
|
|
|
tp->dev = dev;
|
|
raw_spin_lock_init(&tp->lock);
|
|
|
|
regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
/*
|
|
* Make a copy of the families which we can use to hold pointers
|
|
* to the registers.
|
|
*/
|
|
families_len = size_mul(sizeof(*families), tp->nfamilies);
|
|
families = devm_kmemdup(dev, tp->families, families_len, GFP_KERNEL);
|
|
if (!families)
|
|
return -ENOMEM;
|
|
|
|
/* Splice memory resource by chunk per family */
|
|
for (i = 0; i < tp->nfamilies; i++) {
|
|
struct tng_family *family = &families[i];
|
|
|
|
family->regs = regs + family->barno * TNG_FAMILY_LEN;
|
|
}
|
|
|
|
tp->families = families;
|
|
tp->pctldesc = tng_pinctrl_desc;
|
|
tp->pctldesc.name = dev_name(dev);
|
|
tp->pctldesc.pins = tp->pins;
|
|
tp->pctldesc.npins = tp->npins;
|
|
|
|
tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp);
|
|
if (IS_ERR(tp->pctldev))
|
|
return dev_err_probe(dev, PTR_ERR(tp->pctldev),
|
|
"failed to register pinctrl driver\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int devm_tng_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
const struct tng_pinctrl *data;
|
|
|
|
data = device_get_match_data(&pdev->dev);
|
|
if (!data)
|
|
return -ENODATA;
|
|
|
|
return tng_pinctrl_probe(pdev, data);
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(devm_tng_pinctrl_probe, PINCTRL_TANGIER);
|
|
|
|
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
|
MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>");
|
|
MODULE_DESCRIPTION("Intel Tangier pinctrl driver");
|
|
MODULE_LICENSE("GPL");
|