mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-02 08:34:20 +08:00
42b5f40610
The Armada 39x, contrary to its predecessor, has a configurable reference clock frequency, of either 25 Mhz, or 40 Mhz. For the previous SoCs, it was fixed to 25 Mhz and described directly as such in the Device Tree. For Armada 39x, we need to read certain registers to know whether the frequency is 25 or 40 Mhz. Therefore, this commit extends the common mvebu clock code to allow the SoC-specific code to say it wants to register a reference clock, by giving a non-NULL ->get_refclk_freq() function pointer in its coreclk_soc_desc structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
|
|
* Marvell EBU SoC common clock handling
|
|
*
|
|
* Copyright (C) 2012 Marvell
|
|
*
|
|
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
|
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
|
* Andrew Lunn <andrew@lunn.ch>
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#ifndef __CLK_MVEBU_COMMON_H_
|
|
#define __CLK_MVEBU_COMMON_H_
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
extern spinlock_t ctrl_gating_lock;
|
|
|
|
struct device_node;
|
|
|
|
struct coreclk_ratio {
|
|
int id;
|
|
const char *name;
|
|
};
|
|
|
|
struct coreclk_soc_desc {
|
|
u32 (*get_tclk_freq)(void __iomem *sar);
|
|
u32 (*get_cpu_freq)(void __iomem *sar);
|
|
void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
|
|
u32 (*get_refclk_freq)(void __iomem *sar);
|
|
bool (*is_sscg_enabled)(void __iomem *sar);
|
|
u32 (*fix_sscg_deviation)(u32 system_clk);
|
|
const struct coreclk_ratio *ratios;
|
|
int num_ratios;
|
|
};
|
|
|
|
struct clk_gating_soc_desc {
|
|
const char *name;
|
|
const char *parent;
|
|
int bit_idx;
|
|
unsigned long flags;
|
|
};
|
|
|
|
void __init mvebu_coreclk_setup(struct device_node *np,
|
|
const struct coreclk_soc_desc *desc);
|
|
|
|
void __init mvebu_clk_gating_setup(struct device_node *np,
|
|
const struct clk_gating_soc_desc *desc);
|
|
|
|
/*
|
|
* This function is shared among the Kirkwood, Armada 370, Armada XP
|
|
* and Armada 375 SoC
|
|
*/
|
|
u32 kirkwood_fix_sscg_deviation(u32 system_clk);
|
|
#endif
|