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a2faac3986
Similar to commita6c30873ee("ARM: 8989/1: use .fpu assembler directives instead of assembler arguments"). GCC and GNU binutils support setting the "sub arch" via -march=, -Wa,-march, target function attribute, and .arch assembler directive. Clang was missing support for -Wa,-march=, but this was implemented in clang-13. The behavior of both GCC and Clang is to prefer -Wa,-march= over -march= for assembler and assembler-with-cpp sources, but Clang will warn about the -march= being unused. clang: warning: argument unused during compilation: '-march=armv6k' [-Wunused-command-line-argument] Since most assembler is non-conditionally assembled with one sub arch (modulo arch/arm/delay-loop.S which conditionally is assembled as armv4 based on CONFIG_ARCH_RPC, and arch/arm/mach-at91/pm-suspend.S which is conditionally assembled as armv7-a based on CONFIG_CPU_V7), prefer the .arch assembler directive. Add a few more instances found in compile testing as found by Arnd and Nathan. Link:1d51c699b9Link: https://bugs.llvm.org/show_bug.cgi?id=48894 Link: https://github.com/ClangBuiltLinux/linux/issues/1195 Link: https://github.com/ClangBuiltLinux/linux/issues/1315 Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
46 lines
1.2 KiB
ArmAsm
46 lines
1.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "abort-macro.S"
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/*
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* Function: v6_early_abort
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*
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* Params : r2 = pt_regs
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* : r4 = aborted context pc
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* : r5 = aborted context psr
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*
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* Returns : r4 - r11, r13 preserved
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*
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* Purpose : obtain information about current aborted instruction.
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* Note: we read user space. This means we might cause a data
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* abort here if the I-TLB and D-TLB aren't seeing the same
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* picture. Unfortunately, this does happen. We live with it.
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*/
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.arch armv6k
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.align 5
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ENTRY(v6_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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/*
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* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
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*/
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#ifdef CONFIG_ARM_ERRATA_326103
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ldr ip, =0x4107b36
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mrc p15, 0, r3, c0, c0, 0 @ get processor id
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teq ip, r3, lsr #4 @ r0 ARM1136?
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bne 1f
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tst r5, #PSR_J_BIT @ Java?
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tsteq r5, #PSR_T_BIT @ Thumb?
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bne 1f
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bic r1, r1, #1 << 11 @ clear bit 11 of FSR
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ldr r3, [r4] @ read aborted ARM instruction
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ARM_BE8(rev r3, r3)
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teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
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beq 1f @ yes
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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#endif
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1: uaccess_disable ip @ disable userspace access
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b do_DataAbort
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