Dave Jiang 2ec1b17f74 cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment ... 'addr' that contains RAS UE register address is re-assigned to RAS_CAP_CONTROL offset if there are multiple UE errors. Use different addr variable to avoid the reassignment mistake. Fixes: 2905cb5236 ("cxl/pci: Add (hopeful) error handling support") Reported-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/167302318779.580155.15233596744650706167.stgit@djiang5-mobl3.local Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2023-01-09 12:55:54 -08:00
..
core	cxl/region: Fix memdev reuse check	2022-12-08 13:03:47 -08:00
acpi.c	cxl: update names for interleave ways conversion macros	2022-12-05 18:17:16 -08:00
cxl.h	cxl: update names for interleave ways conversion macros	2022-12-05 18:17:16 -08:00
cxlmem.h	cxl/mbox: Add variable output size validation for internal commands	2022-12-06 14:36:02 -08:00
cxlpci.h	cxl/core/regs: Make cxl_map_{component, device}_regs() device generic	2022-12-03 13:40:16 -08:00
Kconfig	cxl/region: Manage CPU caches relative to DPA invalidation events	2022-12-03 00:03:57 -08:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
mem.c	cxl/port: Add RCD endpoint port enumeration	2022-12-05 10:32:26 -08:00
pci.c	cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment	2023-01-09 12:55:54 -08:00
pmem.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00
security.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00