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2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
167 lines
6.0 KiB
Plaintext
167 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
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*/
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/dts-v1/;
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#include "omap3-lilly-a83x.dtsi"
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/ {
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model = "INCOstartec LILLY-DBB056 (DM3730)";
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compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
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};
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&twl {
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vaux2: regulator-vaux2 {
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compatible = "ti,twl4030-vaux2";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-always-on;
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};
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};
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_pins>;
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lan9117_pins: pinmux_lan9117_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */
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>;
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};
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gpio4_pins: pinmux_gpio4_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */
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>;
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};
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gpio5_pins: pinmux_gpio5_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */
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>;
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};
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lcd_pins: pinmux_lcd_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
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OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
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OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
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OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
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OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
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OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
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OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
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OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
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OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
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OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
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OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
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OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
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OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
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OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
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OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
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OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
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OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
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OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
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OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
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OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
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OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
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OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
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>;
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};
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mmc2_pins: pinmux_mmc2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
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OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
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OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
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OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
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OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
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OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
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OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
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OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
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OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
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OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
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OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */
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OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */
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>;
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};
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spi1_pins: pinmux_spi1_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
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OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
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OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
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OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
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>;
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};
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};
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&gpio4 {
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pinctrl-names = "default";
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pinctrl-0 = <&gpio4_pins>;
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};
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&gpio5 {
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pinctrl-names = "default";
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pinctrl-0 = <&gpio5_pins>;
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};
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&mmc2 {
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status = "okay";
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bus-width = <4>;
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vmmc-supply = <&vmmc1>;
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cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */
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wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_pins>;
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ti,dual-volt;
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};
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&mcspi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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};
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&gpmc {
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ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */
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<4 0 0x20000000 0x01000000>,
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<7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */
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ethernet@4,0 {
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compatible = "smsc,lan9117", "smsc,lan9115";
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bank-width = <2>;
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gpmc,mux-add-data = <2>;
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gpmc,cs-on-ns = <10>;
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gpmc,cs-rd-off-ns = <65>;
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gpmc,cs-wr-off-ns = <65>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <10>;
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gpmc,adv-wr-off-ns = <10>;
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gpmc,oe-on-ns = <10>;
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gpmc,oe-off-ns = <65>;
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gpmc,we-on-ns = <10>;
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gpmc,we-off-ns = <65>;
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gpmc,rd-cycle-ns = <100>;
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gpmc,wr-cycle-ns = <100>;
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gpmc,access-ns = <60>;
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gpmc,page-burst-access-ns = <5>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <75>;
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gpmc,wr-data-mux-bus-ns = <15>;
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gpmc,wr-access-ns = <75>;
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gpmc,cycle2cycle-samecsen;
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gpmc,cycle2cycle-diffcsen;
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vddvario-supply = <®_vcc3>;
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vdd33a-supply = <®_vcc3>;
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reg-io-width = <4>;
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interrupt-parent = <&gpio4>;
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interrupts = <2 0x2>;
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reg = <4 0 0xff>;
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pinctrl-names = "default";
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pinctrl-0 = <&lan9117_pins>;
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phy-mode = "mii";
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smsc,force-internal-phy;
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};
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};
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