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2e4ba0ec97
Allow cxl_await_media_ready() to be mocked for testing purposes rather than carrying the maintenance burden of an indirect function call in the mainline driver. With the move cxl_await_media_ready() can no longer reuse the mailbox timeout override, so add a media_ready_timeout module parameter to the core to backfill. Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/165291688340.1426646.4755627801983775011.stgit@dwillia2-xfh Signed-off-by: Dan Williams <dan.j.williams@intel.com>
145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <cxlpci.h>
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#include <cxlmem.h>
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#include <cxl.h>
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#include "core.h"
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/**
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* DOC: cxl core pci
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*
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* Compute Express Link protocols are layered on top of PCIe. CXL core provides
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* a set of helpers for CXL interactions which occur via PCIe.
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*/
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static unsigned short media_ready_timeout = 60;
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module_param(media_ready_timeout, ushort, 0644);
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MODULE_PARM_DESC(media_ready_timeout, "seconds to wait for media ready");
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struct cxl_walk_context {
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struct pci_bus *bus;
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struct cxl_port *port;
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int type;
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int error;
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int count;
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};
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static int match_add_dports(struct pci_dev *pdev, void *data)
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{
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struct cxl_walk_context *ctx = data;
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struct cxl_port *port = ctx->port;
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int type = pci_pcie_type(pdev);
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struct cxl_register_map map;
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struct cxl_dport *dport;
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u32 lnkcap, port_num;
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int rc;
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if (pdev->bus != ctx->bus)
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return 0;
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if (!pci_is_pcie(pdev))
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return 0;
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if (type != ctx->type)
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return 0;
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if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
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&lnkcap))
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return 0;
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rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
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if (rc)
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dev_dbg(&port->dev, "failed to find component registers\n");
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port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
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dport = devm_cxl_add_dport(port, &pdev->dev, port_num,
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cxl_regmap_to_base(pdev, &map));
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if (IS_ERR(dport)) {
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ctx->error = PTR_ERR(dport);
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return PTR_ERR(dport);
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}
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ctx->count++;
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dev_dbg(&port->dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
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return 0;
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}
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/**
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* devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port
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* @port: cxl_port whose ->uport is the upstream of dports to be enumerated
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*
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* Returns a positive number of dports enumerated or a negative error
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* code.
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*/
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int devm_cxl_port_enumerate_dports(struct cxl_port *port)
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{
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struct pci_bus *bus = cxl_port_to_pci_bus(port);
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struct cxl_walk_context ctx;
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int type;
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if (!bus)
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return -ENXIO;
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if (pci_is_root_bus(bus))
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type = PCI_EXP_TYPE_ROOT_PORT;
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else
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type = PCI_EXP_TYPE_DOWNSTREAM;
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ctx = (struct cxl_walk_context) {
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.port = port,
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.bus = bus,
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.type = type,
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};
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pci_walk_bus(bus, match_add_dports, &ctx);
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if (ctx.count == 0)
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return -ENODEV;
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if (ctx.error)
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return ctx.error;
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return ctx.count;
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_port_enumerate_dports, CXL);
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/*
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* Wait up to @media_ready_timeout for the device to report memory
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* active.
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*/
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int cxl_await_media_ready(struct cxl_dev_state *cxlds)
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{
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struct pci_dev *pdev = to_pci_dev(cxlds->dev);
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int d = cxlds->cxl_dvsec;
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bool active = false;
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u64 md_status;
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int rc, i;
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for (i = media_ready_timeout; i; i--) {
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u32 temp;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &temp);
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if (rc)
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return rc;
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active = FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp);
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if (active)
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break;
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msleep(1000);
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}
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if (!active) {
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dev_err(&pdev->dev,
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"timeout awaiting memory active after %d seconds\n",
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media_ready_timeout);
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return -ETIMEDOUT;
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}
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md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);
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if (!CXLMDEV_READY(md_status))
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return -EIO;
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);
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