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a160e9414d
Unaligned exception handler is needed in configurations with hardware
support for unaligned access when the load/store exception handler is
enabled because such configurations would still raise an exception on
unaligned access through the instruction bus.
Fixes: f29cf77609 ("xtensa: add load/store exception handler")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
574 lines
14 KiB
ArmAsm
574 lines
14 KiB
ArmAsm
/*
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* arch/xtensa/kernel/align.S
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*
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* Handle unalignment and load/store exceptions.
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica, Inc.
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* Copyright (C) 2014 Cadence Design Systems Inc.
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*
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* Rewritten by Chris Zankel <chris@zankel.net>
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*
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* Based on work from Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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* and Marc Gauthier <marc@tensilica.com, marc@alimni.uwaterloo.ca>
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*/
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#include <linux/linkage.h>
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#include <asm/current.h>
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#include <asm/asm-offsets.h>
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#include <asm/asmmacro.h>
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#include <asm/processor.h>
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || defined CONFIG_XTENSA_LOAD_STORE
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#define LOAD_EXCEPTION_HANDLER
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#endif
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#if XCHAL_UNALIGNED_STORE_EXCEPTION || defined CONFIG_XTENSA_LOAD_STORE
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#define STORE_EXCEPTION_HANDLER
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#endif
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#if defined LOAD_EXCEPTION_HANDLER || defined STORE_EXCEPTION_HANDLER
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#define ANY_EXCEPTION_HANDLER
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#endif
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#if XCHAL_HAVE_WINDOWED && defined CONFIG_MMU
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#define UNALIGNED_USER_EXCEPTION
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#endif
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/* Big and little endian 16-bit values are located in
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* different halves of a register. HWORD_START helps to
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* abstract the notion of extracting a 16-bit value from a
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* register.
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* We also have to define new shifting instructions because
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* lsb and msb are on 'opposite' ends in a register for
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* different endian machines.
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*
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* Assume a memory region in ascending address:
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* 0 1 2 3|4 5 6 7
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*
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* When loading one word into a register, the content of that register is:
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* LE 3 2 1 0, 7 6 5 4
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* BE 0 1 2 3, 4 5 6 7
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*
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* Masking the bits of the higher/lower address means:
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* LE X X 0 0, 0 0 X X
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* BE 0 0 X X, X X 0 0
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*
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* Shifting to higher/lower addresses, means:
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* LE shift left / shift right
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* BE shift right / shift left
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*
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* Extracting 16 bits from a 32 bit reg. value to higher/lower address means:
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* LE mask 0 0 X X / shift left
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* BE shift left / mask 0 0 X X
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*/
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#if XCHAL_HAVE_BE
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#define HWORD_START 16
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#define INSN_OP0 28
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#define INSN_T 24
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#define INSN_OP1 16
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.macro __ssa8r r; ssa8l \r; .endm
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.macro __sh r, s; srl \r, \s; .endm
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.macro __sl r, s; sll \r, \s; .endm
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.macro __exth r, s; extui \r, \s, 0, 16; .endm
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.macro __extl r, s; slli \r, \s, 16; .endm
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#else
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#define HWORD_START 0
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#define INSN_OP0 0
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#define INSN_T 4
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#define INSN_OP1 12
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.macro __ssa8r r; ssa8b \r; .endm
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.macro __sh r, s; sll \r, \s; .endm
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.macro __sl r, s; srl \r, \s; .endm
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.macro __exth r, s; slli \r, \s, 16; .endm
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.macro __extl r, s; extui \r, \s, 0, 16; .endm
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#endif
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/*
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* xxxx xxxx = imm8 field
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* yyyy = imm4 field
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* ssss = s field
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* tttt = t field
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*
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* 16 0
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* -------------------
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* L32I.N yyyy ssss tttt 1000
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* S32I.N yyyy ssss tttt 1001
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*
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* 23 0
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* -----------------------------
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* L8UI xxxx xxxx 0000 ssss tttt 0010
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* L16UI xxxx xxxx 0001 ssss tttt 0010
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* L32I xxxx xxxx 0010 ssss tttt 0010
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* XXX 0011 ssss tttt 0010
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* XXX 0100 ssss tttt 0010
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* S16I xxxx xxxx 0101 ssss tttt 0010
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* S32I xxxx xxxx 0110 ssss tttt 0010
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* XXX 0111 ssss tttt 0010
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* XXX 1000 ssss tttt 0010
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* L16SI xxxx xxxx 1001 ssss tttt 0010
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* XXX 1010 0010
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* **L32AI xxxx xxxx 1011 ssss tttt 0010 unsupported
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* XXX 1100 0010
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* XXX 1101 0010
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* XXX 1110 0010
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* **S32RI xxxx xxxx 1111 ssss tttt 0010 unsupported
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* -----------------------------
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* ^ ^ ^
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* sub-opcode (NIBBLE_R) -+ | |
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* t field (NIBBLE_T) -----------+ |
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* major opcode (NIBBLE_OP0) --------------+
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*/
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#define OP0_L32I_N 0x8 /* load immediate narrow */
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#define OP0_S32I_N 0x9 /* store immediate narrow */
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#define OP0_LSAI 0x2 /* load/store */
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#define OP1_SI_MASK 0x4 /* OP1 bit set for stores */
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#define OP1_SI_BIT 2 /* OP1 bit number for stores */
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#define OP1_L8UI 0x0
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#define OP1_L32I 0x2
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#define OP1_L16UI 0x1
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#define OP1_L16SI 0x9
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#define OP1_L32AI 0xb
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#define OP1_S32I 0x6
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#define OP1_S16I 0x5
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#define OP1_S32RI 0xf
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/*
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* Entry condition:
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*
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* a0: trashed, original value saved on stack (PT_AREG0)
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* a1: a1
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* a2: new stack pointer, original in DEPC
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* a3: a3
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* depc: a2, original value saved on stack (PT_DEPC)
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* excsave_1: dispatch table
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*
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* PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
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* < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
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*/
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.literal_position
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#ifdef CONFIG_XTENSA_LOAD_STORE
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ENTRY(fast_load_store)
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call0 .Lsave_and_load_instruction
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/* Analyze the instruction (load or store?). */
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extui a0, a4, INSN_OP0, 4 # get insn.op0 nibble
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#if XCHAL_HAVE_DENSITY
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_beqi a0, OP0_L32I_N, 1f # L32I.N, jump
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#endif
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bnei a0, OP0_LSAI, .Linvalid_instruction
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/* 'store indicator bit' set, jump */
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bbsi.l a4, OP1_SI_BIT + INSN_OP1, .Linvalid_instruction
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1:
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movi a3, ~3
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and a3, a3, a8 # align memory address
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__ssa8 a8
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#ifdef CONFIG_MMU
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/* l32e can't be used here even when it's available. */
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/* TODO access_ok(a3) could be used here */
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j .Linvalid_instruction
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#endif
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l32i a5, a3, 0
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l32i a6, a3, 4
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__src_b a3, a5, a6 # a3 has the data word
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#if XCHAL_HAVE_DENSITY
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addi a7, a7, 2 # increment PC (assume 16-bit insn)
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_beqi a0, OP0_L32I_N, .Lload_w# l32i.n: jump
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addi a7, a7, 1
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#else
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addi a7, a7, 3
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#endif
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extui a5, a4, INSN_OP1, 4
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_beqi a5, OP1_L32I, .Lload_w
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bnei a5, OP1_L8UI, .Lload16
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extui a3, a3, 0, 8
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j .Lload_w
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ENDPROC(fast_load_store)
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#endif
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/*
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* Entry condition:
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*
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* a0: trashed, original value saved on stack (PT_AREG0)
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* a1: a1
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* a2: new stack pointer, original in DEPC
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* a3: a3
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* depc: a2, original value saved on stack (PT_DEPC)
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* excsave_1: dispatch table
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*
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* PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
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* < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
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*/
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#ifdef ANY_EXCEPTION_HANDLER
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ENTRY(fast_unaligned)
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call0 .Lsave_and_load_instruction
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/* Analyze the instruction (load or store?). */
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extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble
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#if XCHAL_HAVE_DENSITY
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_beqi a5, OP0_L32I_N, .Lload # L32I.N, jump
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addi a6, a5, -OP0_S32I_N
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_beqz a6, .Lstore # S32I.N, do a store
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#endif
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/* 'store indicator bit' not set, jump */
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_bbci.l a4, OP1_SI_BIT + INSN_OP1, .Lload
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#ifdef STORE_EXCEPTION_HANDLER
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/* Store: Jump to table entry to get the value in the source register.*/
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.Lstore:movi a5, .Lstore_table # table
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extui a6, a4, INSN_T, 4 # get source register
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addx8 a5, a6, a5
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jx a5 # jump into table
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#endif
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#ifdef LOAD_EXCEPTION_HANDLER
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/* Load: Load memory address. */
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.Lload: movi a3, ~3
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and a3, a3, a8 # align memory address
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__ssa8 a8
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#ifdef UNALIGNED_USER_EXCEPTION
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addi a3, a3, 8
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l32e a5, a3, -8
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l32e a6, a3, -4
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#else
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l32i a5, a3, 0
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l32i a6, a3, 4
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#endif
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__src_b a3, a5, a6 # a3 has the data word
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#if XCHAL_HAVE_DENSITY
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addi a7, a7, 2 # increment PC (assume 16-bit insn)
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extui a5, a4, INSN_OP0, 4
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_beqi a5, OP0_L32I_N, .Lload_w# l32i.n: jump
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addi a7, a7, 1
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#else
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addi a7, a7, 3
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#endif
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extui a5, a4, INSN_OP1, 4
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_beqi a5, OP1_L32I, .Lload_w # l32i: jump
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#endif
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#ifdef LOAD_EXCEPTION_HANDLER
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.Lload16:
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extui a3, a3, 0, 16 # extract lower 16 bits
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_beqi a5, OP1_L16UI, .Lload_w
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addi a5, a5, -OP1_L16SI
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_bnez a5, .Linvalid_instruction
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/* sign extend value */
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#if XCHAL_HAVE_SEXT
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sext a3, a3, 15
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#else
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slli a3, a3, 16
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srai a3, a3, 16
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#endif
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/* Set target register. */
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.Lload_w:
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extui a4, a4, INSN_T, 4 # extract target register
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movi a5, .Lload_table
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addx8 a4, a4, a5
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jx a4 # jump to entry for target register
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.align 8
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.Lload_table:
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s32i a3, a2, PT_AREG0; _j .Lexit; .align 8
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mov a1, a3; _j .Lexit; .align 8 # fishy??
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s32i a3, a2, PT_AREG2; _j .Lexit; .align 8
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s32i a3, a2, PT_AREG3; _j .Lexit; .align 8
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s32i a3, a2, PT_AREG4; _j .Lexit; .align 8
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s32i a3, a2, PT_AREG5; _j .Lexit; .align 8
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s32i a3, a2, PT_AREG6; _j .Lexit; .align 8
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s32i a3, a2, PT_AREG7; _j .Lexit; .align 8
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s32i a3, a2, PT_AREG8; _j .Lexit; .align 8
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mov a9, a3 ; _j .Lexit; .align 8
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mov a10, a3 ; _j .Lexit; .align 8
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mov a11, a3 ; _j .Lexit; .align 8
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mov a12, a3 ; _j .Lexit; .align 8
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mov a13, a3 ; _j .Lexit; .align 8
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mov a14, a3 ; _j .Lexit; .align 8
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mov a15, a3 ; _j .Lexit; .align 8
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#endif
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#ifdef STORE_EXCEPTION_HANDLER
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.Lstore_table:
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l32i a3, a2, PT_AREG0; _j .Lstore_w; .align 8
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mov a3, a1; _j .Lstore_w; .align 8 # fishy??
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l32i a3, a2, PT_AREG2; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG3; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG4; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG5; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG6; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG7; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG8; _j .Lstore_w; .align 8
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mov a3, a9 ; _j .Lstore_w; .align 8
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mov a3, a10 ; _j .Lstore_w; .align 8
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mov a3, a11 ; _j .Lstore_w; .align 8
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mov a3, a12 ; _j .Lstore_w; .align 8
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mov a3, a13 ; _j .Lstore_w; .align 8
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mov a3, a14 ; _j .Lstore_w; .align 8
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mov a3, a15 ; _j .Lstore_w; .align 8
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#endif
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/* We cannot handle this exception. */
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.extern _kernel_exception
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.Linvalid_instruction:
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movi a4, 0
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rsr a3, excsave1
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s32i a4, a3, EXC_TABLE_FIXUP
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/* Restore a4...a8 and SAR, set SP, and jump to default exception. */
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l32i a0, a2, PT_SAR
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l32i a8, a2, PT_AREG8
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l32i a7, a2, PT_AREG7
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l32i a6, a2, PT_AREG6
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l32i a5, a2, PT_AREG5
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l32i a4, a2, PT_AREG4
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wsr a0, sar
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mov a1, a2
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rsr a0, ps
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bbsi.l a0, PS_UM_BIT, 2f # jump if user mode
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movi a0, _kernel_exception
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jx a0
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2: movi a0, _user_exception
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jx a0
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#ifdef STORE_EXCEPTION_HANDLER
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# a7: instruction pointer, a4: instruction, a3: value
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.Lstore_w:
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movi a6, 0 # mask: ffffffff:00000000
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#if XCHAL_HAVE_DENSITY
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addi a7, a7, 2 # incr. PC,assume 16-bit instruction
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extui a5, a4, INSN_OP0, 4 # extract OP0
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addi a5, a5, -OP0_S32I_N
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_beqz a5, 1f # s32i.n: jump
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addi a7, a7, 1 # increment PC, 32-bit instruction
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#else
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addi a7, a7, 3 # increment PC, 32-bit instruction
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#endif
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extui a5, a4, INSN_OP1, 4 # extract OP1
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_beqi a5, OP1_S32I, 1f # jump if 32 bit store
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_bnei a5, OP1_S16I, .Linvalid_instruction
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movi a5, -1
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__extl a3, a3 # get 16-bit value
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__exth a6, a5 # get 16-bit mask ffffffff:ffff0000
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/* Get memory address */
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1:
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movi a4, ~3
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and a4, a4, a8 # align memory address
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/* Insert value into memory */
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movi a5, -1 # mask: ffffffff:XXXX0000
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#ifdef UNALIGNED_USER_EXCEPTION
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addi a4, a4, 8
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#endif
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__ssa8r a8
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__src_b a8, a5, a6 # lo-mask F..F0..0 (BE) 0..0F..F (LE)
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__src_b a6, a6, a5 # hi-mask 0..0F..F (BE) F..F0..0 (LE)
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#ifdef UNALIGNED_USER_EXCEPTION
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l32e a5, a4, -8
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#else
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l32i a5, a4, 0 # load lower address word
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#endif
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and a5, a5, a8 # mask
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__sh a8, a3 # shift value
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or a5, a5, a8 # or with original value
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#ifdef UNALIGNED_USER_EXCEPTION
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s32e a5, a4, -8
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l32e a8, a4, -4
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#else
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s32i a5, a4, 0 # store
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l32i a8, a4, 4 # same for upper address word
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#endif
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__sl a5, a3
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and a6, a8, a6
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or a6, a6, a5
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#ifdef UNALIGNED_USER_EXCEPTION
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s32e a6, a4, -4
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#else
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s32i a6, a4, 4
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#endif
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#endif
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.Lexit:
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#if XCHAL_HAVE_LOOPS
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rsr a4, lend # check if we reached LEND
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bne a7, a4, 1f
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rsr a4, lcount # and LCOUNT != 0
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beqz a4, 1f
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addi a4, a4, -1 # decrement LCOUNT and set
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rsr a7, lbeg # set PC to LBEGIN
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wsr a4, lcount
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#endif
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1: wsr a7, epc1 # skip emulated instruction
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/* Update icount if we're single-stepping in userspace. */
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rsr a4, icountlevel
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beqz a4, 1f
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bgeui a4, LOCKLEVEL + 1, 1f
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rsr a4, icount
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addi a4, a4, 1
|
|
wsr a4, icount
|
|
1:
|
|
movi a4, 0
|
|
rsr a3, excsave1
|
|
s32i a4, a3, EXC_TABLE_FIXUP
|
|
|
|
/* Restore working register */
|
|
|
|
l32i a0, a2, PT_SAR
|
|
l32i a8, a2, PT_AREG8
|
|
l32i a7, a2, PT_AREG7
|
|
l32i a6, a2, PT_AREG6
|
|
l32i a5, a2, PT_AREG5
|
|
l32i a4, a2, PT_AREG4
|
|
l32i a3, a2, PT_AREG3
|
|
|
|
/* restore SAR and return */
|
|
|
|
wsr a0, sar
|
|
l32i a0, a2, PT_AREG0
|
|
l32i a2, a2, PT_AREG2
|
|
rfe
|
|
|
|
.align 4
|
|
.Lsave_and_load_instruction:
|
|
|
|
/* Save some working register */
|
|
|
|
s32i a3, a2, PT_AREG3
|
|
s32i a4, a2, PT_AREG4
|
|
s32i a5, a2, PT_AREG5
|
|
s32i a6, a2, PT_AREG6
|
|
s32i a7, a2, PT_AREG7
|
|
s32i a8, a2, PT_AREG8
|
|
|
|
rsr a4, depc
|
|
s32i a4, a2, PT_AREG2
|
|
|
|
rsr a5, sar
|
|
s32i a5, a2, PT_SAR
|
|
|
|
rsr a3, excsave1
|
|
movi a4, fast_unaligned_fixup
|
|
s32i a4, a3, EXC_TABLE_FIXUP
|
|
|
|
rsr a8, excvaddr # load unaligned memory address
|
|
|
|
/* Now, identify one of the following load/store instructions.
|
|
*
|
|
* The only possible danger of a double exception on the
|
|
* following l32i instructions is kernel code in vmalloc
|
|
* memory. The processor was just executing at the EPC_1
|
|
* address, and indeed, already fetched the instruction. That
|
|
* guarantees a TLB mapping, which hasn't been replaced by
|
|
* this unaligned exception handler that uses only static TLB
|
|
* mappings. However, high-level interrupt handlers might
|
|
* modify TLB entries, so for the generic case, we register a
|
|
* TABLE_FIXUP handler here, too.
|
|
*/
|
|
|
|
/* a3...a6 saved on stack, a2 = SP */
|
|
|
|
/* Extract the instruction that caused the unaligned access. */
|
|
|
|
rsr a7, epc1 # load exception address
|
|
movi a3, ~3
|
|
and a3, a3, a7 # mask lower bits
|
|
|
|
l32i a4, a3, 0 # load 2 words
|
|
l32i a5, a3, 4
|
|
|
|
__ssa8 a7
|
|
__src_b a4, a4, a5 # a4 has the instruction
|
|
|
|
ret
|
|
|
|
ENDPROC(fast_unaligned)
|
|
|
|
ENTRY(fast_unaligned_fixup)
|
|
|
|
l32i a2, a3, EXC_TABLE_DOUBLE_SAVE
|
|
wsr a3, excsave1
|
|
|
|
l32i a8, a2, PT_AREG8
|
|
l32i a7, a2, PT_AREG7
|
|
l32i a6, a2, PT_AREG6
|
|
l32i a5, a2, PT_AREG5
|
|
l32i a4, a2, PT_SAR
|
|
l32i a0, a2, PT_AREG2
|
|
wsr a4, sar
|
|
wsr a0, depc # restore depc and a0
|
|
l32i a4, a2, PT_AREG4
|
|
|
|
rsr a0, exccause
|
|
s32i a0, a2, PT_DEPC # mark as a regular exception
|
|
|
|
rsr a0, ps
|
|
bbsi.l a0, PS_UM_BIT, 1f # jump if user mode
|
|
|
|
rsr a0, exccause
|
|
addx4 a0, a0, a3 # find entry in table
|
|
l32i a0, a0, EXC_TABLE_FAST_KERNEL # load handler
|
|
l32i a3, a2, PT_AREG3
|
|
jx a0
|
|
1:
|
|
rsr a0, exccause
|
|
addx4 a0, a0, a3 # find entry in table
|
|
l32i a0, a0, EXC_TABLE_FAST_USER # load handler
|
|
l32i a3, a2, PT_AREG3
|
|
jx a0
|
|
|
|
ENDPROC(fast_unaligned_fixup)
|
|
#endif
|