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2deea43f38
Enable CL37 AN complete interrupt for DW XPCS. It requires to clear the bit(0) [CL37_ANCMPLT_INTR] of VR_MII_AN_INTR_STS after AN completed. And there is a quirk for Wangxun devices to enable CL37 AN in backplane configurations because of the special hardware design. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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.. | ||
Kconfig | ||
Makefile | ||
pcs-lynx.c | ||
pcs-mtk-lynxi.c | ||
pcs-rzn1-miic.c | ||
pcs-xpcs-nxp.c | ||
pcs-xpcs-wx.c | ||
pcs-xpcs.c | ||
pcs-xpcs.h |