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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
663 lines
17 KiB
C
663 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* PATA driver for Samsung SoCs.
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* Supports CF Interface in True IDE mode. Currently only PIO mode has been
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* implemented; UDMA support has to be added.
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*
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* Based on:
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* PATA driver for AT91SAM9260 Static Memory Controller
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* PATA driver for Toshiba SCC controller
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/libata.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/platform_data/ata-samsung_cf.h>
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#define DRV_NAME "pata_samsung_cf"
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#define DRV_VERSION "0.1"
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#define S3C_CFATA_REG(x) (x)
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#define S3C_CFATA_MUX S3C_CFATA_REG(0x0)
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#define S3C_ATA_CTRL S3C_CFATA_REG(0x0)
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#define S3C_ATA_CMD S3C_CFATA_REG(0x8)
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#define S3C_ATA_IRQ S3C_CFATA_REG(0x10)
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#define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14)
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#define S3C_ATA_CFG S3C_CFATA_REG(0x18)
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#define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c)
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#define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54)
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#define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58)
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#define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c)
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#define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60)
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#define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64)
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#define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68)
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#define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c)
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#define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70)
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#define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74)
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#define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c)
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#define S3C_CFATA_MUX_TRUEIDE 0x01
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#define S3C_ATA_CFG_SWAP 0x40
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#define S3C_ATA_CFG_IORDYEN 0x02
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enum s3c_cpu_type {
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TYPE_S3C64XX,
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TYPE_S5PV210,
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};
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/*
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* struct s3c_ide_info - S3C PATA instance.
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* @clk: The clock resource for this controller.
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* @ide_addr: The area mapped for the hardware registers.
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* @sfr_addr: The area mapped for the special function registers.
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* @irq: The IRQ number we are using.
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* @cpu_type: The exact type of this controller.
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* @fifo_status_reg: The ATA_FIFO_STATUS register offset.
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*/
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struct s3c_ide_info {
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struct clk *clk;
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void __iomem *ide_addr;
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void __iomem *sfr_addr;
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int irq;
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enum s3c_cpu_type cpu_type;
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unsigned int fifo_status_reg;
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};
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static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
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{
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u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
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reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
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writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
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}
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static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
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{
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/* Select true-ide as the internal operating mode */
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writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
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s3c_ide_sfrbase + S3C_CFATA_MUX);
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}
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static unsigned long
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pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
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{
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int t1 = ata->setup;
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int t2 = ata->act8b;
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int t2i = ata->rec8b;
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ulong piotime;
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piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
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return piotime;
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}
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static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct s3c_ide_info *info = ap->host->private_data;
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struct ata_timing timing;
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int cycle_time;
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ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
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ulong piotime;
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/* Enables IORDY if mode requires it */
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if (ata_pio_need_iordy(adev))
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ata_cfg |= S3C_ATA_CFG_IORDYEN;
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else
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ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
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cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
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ata_timing_compute(adev, adev->pio_mode, &timing,
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cycle_time * 1000, 0);
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piotime = pata_s3c_setup_timing(info, &timing);
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writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
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writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
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}
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/*
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* Waits until the IDE controller is able to perform next read/write
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* operation to the disk. Needed for 64XX series boards only.
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*/
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static int wait_for_host_ready(struct s3c_ide_info *info)
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{
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ulong timeout;
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void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
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/* wait for maximum of 20 msec */
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timeout = jiffies + msecs_to_jiffies(20);
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while (time_before(jiffies, timeout)) {
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if ((readl(fifo_reg) >> 28) == 0)
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return 0;
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}
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return -EBUSY;
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}
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/*
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* Writes to one of the task file registers.
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*/
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static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
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{
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struct s3c_ide_info *info = host->private_data;
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wait_for_host_ready(info);
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writeb(addr, reg);
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}
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/*
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* Reads from one of the task file registers.
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*/
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static u8 ata_inb(struct ata_host *host, void __iomem *reg)
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{
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struct s3c_ide_info *info = host->private_data;
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u8 temp;
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wait_for_host_ready(info);
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(void) readb(reg);
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wait_for_host_ready(info);
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temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
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return temp;
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}
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/*
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* pata_s3c_tf_load - send taskfile registers to host controller
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*/
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static void pata_s3c_tf_load(struct ata_port *ap,
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const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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if (tf->ctl != ap->last_ctl) {
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ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
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ap->last_ctl = tf->ctl;
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ata_wait_idle(ap);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
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ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
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ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
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ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
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ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
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}
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if (is_addr) {
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ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
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ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
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ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
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ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
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ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
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}
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if (tf->flags & ATA_TFLAG_DEVICE)
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ata_outb(ap->host, tf->device, ioaddr->device_addr);
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ata_wait_idle(ap);
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}
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/*
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* pata_s3c_tf_read - input device's ATA taskfile shadow registers
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*/
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static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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tf->feature = ata_inb(ap->host, ioaddr->error_addr);
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tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
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tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
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tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
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tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
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tf->device = ata_inb(ap->host, ioaddr->device_addr);
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if (tf->flags & ATA_TFLAG_LBA48) {
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ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
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tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
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tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
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tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
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tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
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tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
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ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
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ap->last_ctl = tf->ctl;
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}
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}
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/*
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* pata_s3c_exec_command - issue ATA command to host controller
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*/
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static void pata_s3c_exec_command(struct ata_port *ap,
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const struct ata_taskfile *tf)
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{
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ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
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ata_sff_pause(ap);
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}
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/*
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* pata_s3c_check_status - Read device status register
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*/
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static u8 pata_s3c_check_status(struct ata_port *ap)
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{
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return ata_inb(ap->host, ap->ioaddr.status_addr);
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}
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/*
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* pata_s3c_check_altstatus - Read alternate device status register
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*/
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static u8 pata_s3c_check_altstatus(struct ata_port *ap)
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{
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return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
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}
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/*
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* pata_s3c_data_xfer - Transfer data by PIO
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*/
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static unsigned int pata_s3c_data_xfer(struct ata_queued_cmd *qc,
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unsigned char *buf, unsigned int buflen, int rw)
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{
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struct ata_port *ap = qc->dev->link->ap;
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struct s3c_ide_info *info = ap->host->private_data;
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void __iomem *data_addr = ap->ioaddr.data_addr;
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unsigned int words = buflen >> 1, i;
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u16 *data_ptr = (u16 *)buf;
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/* Requires wait same as in ata_inb/ata_outb */
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if (rw == READ)
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for (i = 0; i < words; i++, data_ptr++) {
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wait_for_host_ready(info);
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(void) readw(data_addr);
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wait_for_host_ready(info);
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*data_ptr = readw(info->ide_addr
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+ S3C_ATA_PIO_RDATA);
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}
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else
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for (i = 0; i < words; i++, data_ptr++) {
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wait_for_host_ready(info);
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writew(*data_ptr, data_addr);
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}
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if (buflen & 0x01)
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dev_err(ap->dev, "unexpected trailing data\n");
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return words << 1;
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}
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/*
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* pata_s3c_dev_select - Select device on ATA bus
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*/
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static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
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{
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u8 tmp = ATA_DEVICE_OBS;
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if (device != 0)
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tmp |= ATA_DEV1;
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ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
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ata_sff_pause(ap);
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}
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/*
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* pata_s3c_devchk - PATA device presence detection
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*/
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static unsigned int pata_s3c_devchk(struct ata_port *ap,
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unsigned int device)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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u8 nsect, lbal;
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pata_s3c_dev_select(ap, device);
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ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
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ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
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ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
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ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
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ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
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ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
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nsect = ata_inb(ap->host, ioaddr->nsect_addr);
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lbal = ata_inb(ap->host, ioaddr->lbal_addr);
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if ((nsect == 0x55) && (lbal == 0xaa))
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return 1; /* we found a device */
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return 0; /* nothing found */
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}
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/*
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* pata_s3c_wait_after_reset - wait for devices to become ready after reset
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*/
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static int pata_s3c_wait_after_reset(struct ata_link *link,
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unsigned long deadline)
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{
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int rc;
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ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
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/* always check readiness of the master device */
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rc = ata_sff_wait_ready(link, deadline);
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/* -ENODEV means the odd clown forgot the D7 pulldown resistor
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* and TF status is 0xff, bail out on it too.
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*/
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if (rc)
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return rc;
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return 0;
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}
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/*
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* pata_s3c_bus_softreset - PATA device software reset
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*/
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static int pata_s3c_bus_softreset(struct ata_port *ap,
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unsigned long deadline)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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/* software reset. causes dev0 to be selected */
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ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
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udelay(20);
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ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
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udelay(20);
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ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
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ap->last_ctl = ap->ctl;
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return pata_s3c_wait_after_reset(&ap->link, deadline);
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}
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/*
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* pata_s3c_softreset - reset host port via ATA SRST
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*/
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static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
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unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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unsigned int devmask = 0;
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int rc;
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u8 err;
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/* determine if device 0 is present */
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if (pata_s3c_devchk(ap, 0))
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devmask |= (1 << 0);
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/* select device 0 again */
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pata_s3c_dev_select(ap, 0);
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/* issue bus reset */
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rc = pata_s3c_bus_softreset(ap, deadline);
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/* if link is occupied, -ENODEV too is an error */
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if (rc && rc != -ENODEV) {
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ata_link_err(link, "SRST failed (errno=%d)\n", rc);
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return rc;
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}
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/* determine by signature whether we have ATA or ATAPI devices */
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classes[0] = ata_sff_dev_classify(&ap->link.device[0],
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devmask & (1 << 0), &err);
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return 0;
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}
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/*
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* pata_s3c_set_devctl - Write device control register
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*/
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static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
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{
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ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
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}
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static struct scsi_host_template pata_s3c_sht = {
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ATA_PIO_SHT(DRV_NAME),
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};
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static struct ata_port_operations pata_s3c_port_ops = {
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.inherits = &ata_sff_port_ops,
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.sff_check_status = pata_s3c_check_status,
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.sff_check_altstatus = pata_s3c_check_altstatus,
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.sff_tf_load = pata_s3c_tf_load,
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.sff_tf_read = pata_s3c_tf_read,
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.sff_data_xfer = pata_s3c_data_xfer,
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.sff_exec_command = pata_s3c_exec_command,
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.sff_dev_select = pata_s3c_dev_select,
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.sff_set_devctl = pata_s3c_set_devctl,
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.softreset = pata_s3c_softreset,
|
|
.set_piomode = pata_s3c_set_piomode,
|
|
};
|
|
|
|
static struct ata_port_operations pata_s5p_port_ops = {
|
|
.inherits = &ata_sff_port_ops,
|
|
.set_piomode = pata_s3c_set_piomode,
|
|
};
|
|
|
|
static void pata_s3c_enable(void __iomem *s3c_ide_regbase, bool state)
|
|
{
|
|
u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
|
|
temp = state ? (temp | 1) : (temp & ~1);
|
|
writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
|
|
}
|
|
|
|
static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
|
|
{
|
|
struct ata_host *host = dev_instance;
|
|
struct s3c_ide_info *info = host->private_data;
|
|
u32 reg;
|
|
|
|
reg = readl(info->ide_addr + S3C_ATA_IRQ);
|
|
writel(reg, info->ide_addr + S3C_ATA_IRQ);
|
|
|
|
return ata_sff_interrupt(irq, dev_instance);
|
|
}
|
|
|
|
static void pata_s3c_hwinit(struct s3c_ide_info *info,
|
|
struct s3c_ide_platdata *pdata)
|
|
{
|
|
switch (info->cpu_type) {
|
|
case TYPE_S3C64XX:
|
|
/* Configure as big endian */
|
|
pata_s3c_cfg_mode(info->sfr_addr);
|
|
pata_s3c_set_endian(info->ide_addr, 1);
|
|
pata_s3c_enable(info->ide_addr, true);
|
|
msleep(100);
|
|
|
|
/* Remove IRQ Status */
|
|
writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
|
|
writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
|
|
break;
|
|
|
|
case TYPE_S5PV210:
|
|
/* Configure as little endian */
|
|
pata_s3c_set_endian(info->ide_addr, 0);
|
|
pata_s3c_enable(info->ide_addr, true);
|
|
msleep(100);
|
|
|
|
/* Remove IRQ Status */
|
|
writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
|
|
writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
|
|
break;
|
|
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static int __init pata_s3c_probe(struct platform_device *pdev)
|
|
{
|
|
struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev);
|
|
struct device *dev = &pdev->dev;
|
|
struct s3c_ide_info *info;
|
|
struct resource *res;
|
|
struct ata_port *ap;
|
|
struct ata_host *host;
|
|
enum s3c_cpu_type cpu_type;
|
|
int ret;
|
|
|
|
cpu_type = platform_get_device_id(pdev)->driver_data;
|
|
|
|
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
|
|
if (!info)
|
|
return -ENOMEM;
|
|
|
|
info->irq = platform_get_irq(pdev, 0);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
info->ide_addr = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(info->ide_addr))
|
|
return PTR_ERR(info->ide_addr);
|
|
|
|
info->clk = devm_clk_get(&pdev->dev, "cfcon");
|
|
if (IS_ERR(info->clk)) {
|
|
dev_err(dev, "failed to get access to cf controller clock\n");
|
|
ret = PTR_ERR(info->clk);
|
|
info->clk = NULL;
|
|
return ret;
|
|
}
|
|
|
|
clk_enable(info->clk);
|
|
|
|
/* init ata host */
|
|
host = ata_host_alloc(dev, 1);
|
|
if (!host) {
|
|
dev_err(dev, "failed to allocate ide host\n");
|
|
ret = -ENOMEM;
|
|
goto stop_clk;
|
|
}
|
|
|
|
ap = host->ports[0];
|
|
ap->pio_mask = ATA_PIO4;
|
|
|
|
if (cpu_type == TYPE_S3C64XX) {
|
|
ap->ops = &pata_s3c_port_ops;
|
|
info->sfr_addr = info->ide_addr + 0x1800;
|
|
info->ide_addr += 0x1900;
|
|
info->fifo_status_reg = 0x94;
|
|
} else {
|
|
ap->ops = &pata_s5p_port_ops;
|
|
info->fifo_status_reg = 0x84;
|
|
}
|
|
|
|
info->cpu_type = cpu_type;
|
|
|
|
if (info->irq <= 0) {
|
|
ap->flags |= ATA_FLAG_PIO_POLLING;
|
|
info->irq = 0;
|
|
ata_port_desc(ap, "no IRQ, using PIO polling\n");
|
|
}
|
|
|
|
ap->ioaddr.cmd_addr = info->ide_addr + S3C_ATA_CMD;
|
|
ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
|
|
ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
|
|
ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
|
|
ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
|
|
ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
|
|
ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
|
|
ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
|
|
ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
|
|
ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
|
|
ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
|
|
ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
|
|
ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
|
|
|
|
ata_port_desc(ap, "mmio cmd 0x%llx ",
|
|
(unsigned long long)res->start);
|
|
|
|
host->private_data = info;
|
|
|
|
if (pdata && pdata->setup_gpio)
|
|
pdata->setup_gpio();
|
|
|
|
/* Set endianness and enable the interface */
|
|
pata_s3c_hwinit(info, pdata);
|
|
|
|
ret = ata_host_activate(host, info->irq,
|
|
info->irq ? pata_s3c_irq : NULL,
|
|
0, &pata_s3c_sht);
|
|
if (ret)
|
|
goto stop_clk;
|
|
|
|
return 0;
|
|
|
|
stop_clk:
|
|
clk_disable(info->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int __exit pata_s3c_remove(struct platform_device *pdev)
|
|
{
|
|
struct ata_host *host = platform_get_drvdata(pdev);
|
|
struct s3c_ide_info *info = host->private_data;
|
|
|
|
ata_host_detach(host);
|
|
|
|
clk_disable(info->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int pata_s3c_suspend(struct device *dev)
|
|
{
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
|
|
return ata_host_suspend(host, PMSG_SUSPEND);
|
|
}
|
|
|
|
static int pata_s3c_resume(struct device *dev)
|
|
{
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
struct s3c_ide_platdata *pdata = dev_get_platdata(dev);
|
|
struct s3c_ide_info *info = host->private_data;
|
|
|
|
pata_s3c_hwinit(info, pdata);
|
|
ata_host_resume(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops pata_s3c_pm_ops = {
|
|
.suspend = pata_s3c_suspend,
|
|
.resume = pata_s3c_resume,
|
|
};
|
|
#endif
|
|
|
|
/* driver device registration */
|
|
static const struct platform_device_id pata_s3c_driver_ids[] = {
|
|
{
|
|
.name = "s3c64xx-pata",
|
|
.driver_data = TYPE_S3C64XX,
|
|
}, {
|
|
.name = "s5pv210-pata",
|
|
.driver_data = TYPE_S5PV210,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
|
|
|
|
static struct platform_driver pata_s3c_driver = {
|
|
.remove = __exit_p(pata_s3c_remove),
|
|
.id_table = pata_s3c_driver_ids,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.pm = &pata_s3c_pm_ops,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(pata_s3c_driver, pata_s3c_probe);
|
|
|
|
MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
|
|
MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION(DRV_VERSION);
|