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c5f2d5645f
Add a dedicated helper for converting a root hpa to a shadow page in anticipation of using a "dummy" root to handle the scenario where KVM needs to load a valid shadow root (from hardware's perspective), but the guest doesn't have a visible root to shadow. Similar to PAE roots, the dummy root won't have an associated kvm_mmu_page and will need special handling when finding a shadow page given a root. Opportunistically retrieve the root shadow page in kvm_mmu_sync_roots() *after* verifying the root is unsync (the dummy root can never be unsync). Link: https://lore.kernel.org/r/20230729005200.1057358-2-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
501 lines
18 KiB
C
501 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#ifndef KVM_X86_MMU_SPTE_H
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#define KVM_X86_MMU_SPTE_H
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#include "mmu_internal.h"
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/*
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* A MMU present SPTE is backed by actual memory and may or may not be present
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* in hardware. E.g. MMIO SPTEs are not considered present. Use bit 11, as it
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* is ignored by all flavors of SPTEs and checking a low bit often generates
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* better code than for a high bit, e.g. 56+. MMU present checks are pervasive
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* enough that the improved code generation is noticeable in KVM's footprint.
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*/
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#define SPTE_MMU_PRESENT_MASK BIT_ULL(11)
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/*
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* TDP SPTES (more specifically, EPT SPTEs) may not have A/D bits, and may also
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* be restricted to using write-protection (for L2 when CPU dirty logging, i.e.
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* PML, is enabled). Use bits 52 and 53 to hold the type of A/D tracking that
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* is must be employed for a given TDP SPTE.
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*
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* Note, the "enabled" mask must be '0', as bits 62:52 are _reserved_ for PAE
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* paging, including NPT PAE. This scheme works because legacy shadow paging
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* is guaranteed to have A/D bits and write-protection is forced only for
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* TDP with CPU dirty logging (PML). If NPT ever gains PML-like support, it
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* must be restricted to 64-bit KVM.
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*/
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#define SPTE_TDP_AD_SHIFT 52
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#define SPTE_TDP_AD_MASK (3ULL << SPTE_TDP_AD_SHIFT)
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#define SPTE_TDP_AD_ENABLED (0ULL << SPTE_TDP_AD_SHIFT)
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#define SPTE_TDP_AD_DISABLED (1ULL << SPTE_TDP_AD_SHIFT)
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#define SPTE_TDP_AD_WRPROT_ONLY (2ULL << SPTE_TDP_AD_SHIFT)
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static_assert(SPTE_TDP_AD_ENABLED == 0);
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#ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
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#define SPTE_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
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#else
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#define SPTE_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
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#endif
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#define SPTE_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
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| shadow_x_mask | shadow_nx_mask | shadow_me_mask)
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#define ACC_EXEC_MASK 1
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#define ACC_WRITE_MASK PT_WRITABLE_MASK
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#define ACC_USER_MASK PT_USER_MASK
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#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
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/* The mask for the R/X bits in EPT PTEs */
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#define SPTE_EPT_READABLE_MASK 0x1ull
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#define SPTE_EPT_EXECUTABLE_MASK 0x4ull
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#define SPTE_LEVEL_BITS 9
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#define SPTE_LEVEL_SHIFT(level) __PT_LEVEL_SHIFT(level, SPTE_LEVEL_BITS)
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#define SPTE_INDEX(address, level) __PT_INDEX(address, level, SPTE_LEVEL_BITS)
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#define SPTE_ENT_PER_PAGE __PT_ENT_PER_PAGE(SPTE_LEVEL_BITS)
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/*
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* The mask/shift to use for saving the original R/X bits when marking the PTE
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* as not-present for access tracking purposes. We do not save the W bit as the
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* PTEs being access tracked also need to be dirty tracked, so the W bit will be
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* restored only when a write is attempted to the page. This mask obviously
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* must not overlap the A/D type mask.
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*/
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#define SHADOW_ACC_TRACK_SAVED_BITS_MASK (SPTE_EPT_READABLE_MASK | \
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SPTE_EPT_EXECUTABLE_MASK)
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#define SHADOW_ACC_TRACK_SAVED_BITS_SHIFT 54
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#define SHADOW_ACC_TRACK_SAVED_MASK (SHADOW_ACC_TRACK_SAVED_BITS_MASK << \
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SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
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static_assert(!(SPTE_TDP_AD_MASK & SHADOW_ACC_TRACK_SAVED_MASK));
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/*
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* {DEFAULT,EPT}_SPTE_{HOST,MMU}_WRITABLE are used to keep track of why a given
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* SPTE is write-protected. See is_writable_pte() for details.
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*/
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/* Bits 9 and 10 are ignored by all non-EPT PTEs. */
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#define DEFAULT_SPTE_HOST_WRITABLE BIT_ULL(9)
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#define DEFAULT_SPTE_MMU_WRITABLE BIT_ULL(10)
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/*
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* Low ignored bits are at a premium for EPT, use high ignored bits, taking care
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* to not overlap the A/D type mask or the saved access bits of access-tracked
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* SPTEs when A/D bits are disabled.
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*/
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#define EPT_SPTE_HOST_WRITABLE BIT_ULL(57)
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#define EPT_SPTE_MMU_WRITABLE BIT_ULL(58)
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static_assert(!(EPT_SPTE_HOST_WRITABLE & SPTE_TDP_AD_MASK));
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static_assert(!(EPT_SPTE_MMU_WRITABLE & SPTE_TDP_AD_MASK));
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static_assert(!(EPT_SPTE_HOST_WRITABLE & SHADOW_ACC_TRACK_SAVED_MASK));
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static_assert(!(EPT_SPTE_MMU_WRITABLE & SHADOW_ACC_TRACK_SAVED_MASK));
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/* Defined only to keep the above static asserts readable. */
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#undef SHADOW_ACC_TRACK_SAVED_MASK
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/*
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* Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
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* the memslots generation and is derived as follows:
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*
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* Bits 0-7 of the MMIO generation are propagated to spte bits 3-10
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* Bits 8-18 of the MMIO generation are propagated to spte bits 52-62
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*
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* The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
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* the MMIO generation number, as doing so would require stealing a bit from
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* the "real" generation number and thus effectively halve the maximum number
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* of MMIO generations that can be handled before encountering a wrap (which
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* requires a full MMU zap). The flag is instead explicitly queried when
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* checking for MMIO spte cache hits.
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*/
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#define MMIO_SPTE_GEN_LOW_START 3
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#define MMIO_SPTE_GEN_LOW_END 10
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#define MMIO_SPTE_GEN_HIGH_START 52
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#define MMIO_SPTE_GEN_HIGH_END 62
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#define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
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MMIO_SPTE_GEN_LOW_START)
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#define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
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MMIO_SPTE_GEN_HIGH_START)
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static_assert(!(SPTE_MMU_PRESENT_MASK &
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(MMIO_SPTE_GEN_LOW_MASK | MMIO_SPTE_GEN_HIGH_MASK)));
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/*
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* The SPTE MMIO mask must NOT overlap the MMIO generation bits or the
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* MMU-present bit. The generation obviously co-exists with the magic MMIO
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* mask/value, and MMIO SPTEs are considered !MMU-present.
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*
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* The SPTE MMIO mask is allowed to use hardware "present" bits (i.e. all EPT
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* RWX bits), all physical address bits (legal PA bits are used for "fast" MMIO
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* and so they're off-limits for generation; additional checks ensure the mask
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* doesn't overlap legal PA bits), and bit 63 (carved out for future usage).
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*/
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#define SPTE_MMIO_ALLOWED_MASK (BIT_ULL(63) | GENMASK_ULL(51, 12) | GENMASK_ULL(2, 0))
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static_assert(!(SPTE_MMIO_ALLOWED_MASK &
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(SPTE_MMU_PRESENT_MASK | MMIO_SPTE_GEN_LOW_MASK | MMIO_SPTE_GEN_HIGH_MASK)));
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#define MMIO_SPTE_GEN_LOW_BITS (MMIO_SPTE_GEN_LOW_END - MMIO_SPTE_GEN_LOW_START + 1)
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#define MMIO_SPTE_GEN_HIGH_BITS (MMIO_SPTE_GEN_HIGH_END - MMIO_SPTE_GEN_HIGH_START + 1)
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/* remember to adjust the comment above as well if you change these */
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static_assert(MMIO_SPTE_GEN_LOW_BITS == 8 && MMIO_SPTE_GEN_HIGH_BITS == 11);
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#define MMIO_SPTE_GEN_LOW_SHIFT (MMIO_SPTE_GEN_LOW_START - 0)
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#define MMIO_SPTE_GEN_HIGH_SHIFT (MMIO_SPTE_GEN_HIGH_START - MMIO_SPTE_GEN_LOW_BITS)
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#define MMIO_SPTE_GEN_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0)
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extern u64 __read_mostly shadow_host_writable_mask;
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extern u64 __read_mostly shadow_mmu_writable_mask;
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extern u64 __read_mostly shadow_nx_mask;
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extern u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
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extern u64 __read_mostly shadow_user_mask;
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extern u64 __read_mostly shadow_accessed_mask;
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extern u64 __read_mostly shadow_dirty_mask;
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extern u64 __read_mostly shadow_mmio_value;
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extern u64 __read_mostly shadow_mmio_mask;
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extern u64 __read_mostly shadow_mmio_access_mask;
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extern u64 __read_mostly shadow_present_mask;
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extern u64 __read_mostly shadow_memtype_mask;
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extern u64 __read_mostly shadow_me_value;
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extern u64 __read_mostly shadow_me_mask;
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/*
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* SPTEs in MMUs without A/D bits are marked with SPTE_TDP_AD_DISABLED;
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* shadow_acc_track_mask is the set of bits to be cleared in non-accessed
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* pages.
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*/
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extern u64 __read_mostly shadow_acc_track_mask;
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/*
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* This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
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* to guard against L1TF attacks.
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*/
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extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
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/*
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* The number of high-order 1 bits to use in the mask above.
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*/
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#define SHADOW_NONPRESENT_OR_RSVD_MASK_LEN 5
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/*
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* If a thread running without exclusive control of the MMU lock must perform a
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* multi-part operation on an SPTE, it can set the SPTE to REMOVED_SPTE as a
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* non-present intermediate value. Other threads which encounter this value
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* should not modify the SPTE.
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*
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* Use a semi-arbitrary value that doesn't set RWX bits, i.e. is not-present on
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* both AMD and Intel CPUs, and doesn't set PFN bits, i.e. doesn't create a L1TF
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* vulnerability. Use only low bits to avoid 64-bit immediates.
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*
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* Only used by the TDP MMU.
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*/
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#define REMOVED_SPTE 0x5a0ULL
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/* Removed SPTEs must not be misconstrued as shadow present PTEs. */
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static_assert(!(REMOVED_SPTE & SPTE_MMU_PRESENT_MASK));
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static inline bool is_removed_spte(u64 spte)
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{
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return spte == REMOVED_SPTE;
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}
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/* Get an SPTE's index into its parent's page table (and the spt array). */
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static inline int spte_index(u64 *sptep)
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{
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return ((unsigned long)sptep / sizeof(*sptep)) & (SPTE_ENT_PER_PAGE - 1);
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}
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/*
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* In some cases, we need to preserve the GFN of a non-present or reserved
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* SPTE when we usurp the upper five bits of the physical address space to
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* defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
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* shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
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* left into the reserved bits, i.e. the GFN in the SPTE will be split into
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* high and low parts. This mask covers the lower bits of the GFN.
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*/
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extern u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
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static inline struct kvm_mmu_page *to_shadow_page(hpa_t shadow_page)
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{
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struct page *page = pfn_to_page((shadow_page) >> PAGE_SHIFT);
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return (struct kvm_mmu_page *)page_private(page);
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}
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static inline struct kvm_mmu_page *spte_to_child_sp(u64 spte)
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{
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return to_shadow_page(spte & SPTE_BASE_ADDR_MASK);
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}
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static inline struct kvm_mmu_page *sptep_to_sp(u64 *sptep)
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{
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return to_shadow_page(__pa(sptep));
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}
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static inline struct kvm_mmu_page *root_to_sp(hpa_t root)
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{
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/*
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* The "root" may be a special root, e.g. a PAE entry, treat it as a
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* SPTE to ensure any non-PA bits are dropped.
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*/
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return spte_to_child_sp(root);
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}
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static inline bool is_mmio_spte(u64 spte)
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{
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return (spte & shadow_mmio_mask) == shadow_mmio_value &&
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likely(enable_mmio_caching);
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}
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static inline bool is_shadow_present_pte(u64 pte)
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{
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return !!(pte & SPTE_MMU_PRESENT_MASK);
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}
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/*
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* Returns true if A/D bits are supported in hardware and are enabled by KVM.
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* When enabled, KVM uses A/D bits for all non-nested MMUs. Because L1 can
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* disable A/D bits in EPTP12, SP and SPTE variants are needed to handle the
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* scenario where KVM is using A/D bits for L1, but not L2.
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*/
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static inline bool kvm_ad_enabled(void)
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{
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return !!shadow_accessed_mask;
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}
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static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
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{
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return sp->role.ad_disabled;
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}
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static inline bool spte_ad_enabled(u64 spte)
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{
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KVM_MMU_WARN_ON(!is_shadow_present_pte(spte));
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return (spte & SPTE_TDP_AD_MASK) != SPTE_TDP_AD_DISABLED;
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}
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static inline bool spte_ad_need_write_protect(u64 spte)
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{
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KVM_MMU_WARN_ON(!is_shadow_present_pte(spte));
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/*
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* This is benign for non-TDP SPTEs as SPTE_TDP_AD_ENABLED is '0',
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* and non-TDP SPTEs will never set these bits. Optimize for 64-bit
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* TDP and do the A/D type check unconditionally.
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*/
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return (spte & SPTE_TDP_AD_MASK) != SPTE_TDP_AD_ENABLED;
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}
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static inline u64 spte_shadow_accessed_mask(u64 spte)
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{
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KVM_MMU_WARN_ON(!is_shadow_present_pte(spte));
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return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
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}
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static inline u64 spte_shadow_dirty_mask(u64 spte)
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{
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KVM_MMU_WARN_ON(!is_shadow_present_pte(spte));
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return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
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}
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static inline bool is_access_track_spte(u64 spte)
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{
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return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
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}
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static inline bool is_large_pte(u64 pte)
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{
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return pte & PT_PAGE_SIZE_MASK;
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}
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static inline bool is_last_spte(u64 pte, int level)
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{
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return (level == PG_LEVEL_4K) || is_large_pte(pte);
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}
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static inline bool is_executable_pte(u64 spte)
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{
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return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
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}
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static inline kvm_pfn_t spte_to_pfn(u64 pte)
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{
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return (pte & SPTE_BASE_ADDR_MASK) >> PAGE_SHIFT;
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}
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static inline bool is_accessed_spte(u64 spte)
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{
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u64 accessed_mask = spte_shadow_accessed_mask(spte);
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return accessed_mask ? spte & accessed_mask
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: !is_access_track_spte(spte);
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}
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static inline bool is_dirty_spte(u64 spte)
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{
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u64 dirty_mask = spte_shadow_dirty_mask(spte);
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return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
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}
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static inline u64 get_rsvd_bits(struct rsvd_bits_validate *rsvd_check, u64 pte,
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int level)
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{
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int bit7 = (pte >> 7) & 1;
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return rsvd_check->rsvd_bits_mask[bit7][level-1];
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}
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static inline bool __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check,
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u64 pte, int level)
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{
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return pte & get_rsvd_bits(rsvd_check, pte, level);
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}
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static inline bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check,
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u64 pte)
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{
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return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
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}
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static __always_inline bool is_rsvd_spte(struct rsvd_bits_validate *rsvd_check,
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u64 spte, int level)
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{
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return __is_bad_mt_xwr(rsvd_check, spte) ||
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__is_rsvd_bits_set(rsvd_check, spte, level);
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}
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/*
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* A shadow-present leaf SPTE may be non-writable for 4 possible reasons:
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*
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* 1. To intercept writes for dirty logging. KVM write-protects huge pages
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* so that they can be split down into the dirty logging
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* granularity (4KiB) whenever the guest writes to them. KVM also
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* write-protects 4KiB pages so that writes can be recorded in the dirty log
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* (e.g. if not using PML). SPTEs are write-protected for dirty logging
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* during the VM-iotcls that enable dirty logging.
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*
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* 2. To intercept writes to guest page tables that KVM is shadowing. When a
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* guest writes to its page table the corresponding shadow page table will
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* be marked "unsync". That way KVM knows which shadow page tables need to
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* be updated on the next TLB flush, INVLPG, etc. and which do not.
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*
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* 3. To prevent guest writes to read-only memory, such as for memory in a
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* read-only memslot or guest memory backed by a read-only VMA. Writes to
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* such pages are disallowed entirely.
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*
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* 4. To emulate the Accessed bit for SPTEs without A/D bits. Note, in this
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* case, the SPTE is access-protected, not just write-protected!
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*
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* For cases #1 and #4, KVM can safely make such SPTEs writable without taking
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* mmu_lock as capturing the Accessed/Dirty state doesn't require taking it.
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* To differentiate #1 and #4 from #2 and #3, KVM uses two software-only bits
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* in the SPTE:
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*
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* shadow_mmu_writable_mask, aka MMU-writable -
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* Cleared on SPTEs that KVM is currently write-protecting for shadow paging
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* purposes (case 2 above).
|
|
*
|
|
* shadow_host_writable_mask, aka Host-writable -
|
|
* Cleared on SPTEs that are not host-writable (case 3 above)
|
|
*
|
|
* Note, not all possible combinations of PT_WRITABLE_MASK,
|
|
* shadow_mmu_writable_mask, and shadow_host_writable_mask are valid. A given
|
|
* SPTE can be in only one of the following states, which map to the
|
|
* aforementioned 3 cases:
|
|
*
|
|
* shadow_host_writable_mask | shadow_mmu_writable_mask | PT_WRITABLE_MASK
|
|
* ------------------------- | ------------------------ | ----------------
|
|
* 1 | 1 | 1 (writable)
|
|
* 1 | 1 | 0 (case 1)
|
|
* 1 | 0 | 0 (case 2)
|
|
* 0 | 0 | 0 (case 3)
|
|
*
|
|
* The valid combinations of these bits are checked by
|
|
* check_spte_writable_invariants() whenever an SPTE is modified.
|
|
*
|
|
* Clearing the MMU-writable bit is always done under the MMU lock and always
|
|
* accompanied by a TLB flush before dropping the lock to avoid corrupting the
|
|
* shadow page tables between vCPUs. Write-protecting an SPTE for dirty logging
|
|
* (which does not clear the MMU-writable bit), does not flush TLBs before
|
|
* dropping the lock, as it only needs to synchronize guest writes with the
|
|
* dirty bitmap. Similarly, making the SPTE inaccessible (and non-writable) for
|
|
* access-tracking via the clear_young() MMU notifier also does not flush TLBs.
|
|
*
|
|
* So, there is the problem: clearing the MMU-writable bit can encounter a
|
|
* write-protected SPTE while CPUs still have writable mappings for that SPTE
|
|
* cached in their TLB. To address this, KVM always flushes TLBs when
|
|
* write-protecting SPTEs if the MMU-writable bit is set on the old SPTE.
|
|
*
|
|
* The Host-writable bit is not modified on present SPTEs, it is only set or
|
|
* cleared when an SPTE is first faulted in from non-present and then remains
|
|
* immutable.
|
|
*/
|
|
static inline bool is_writable_pte(unsigned long pte)
|
|
{
|
|
return pte & PT_WRITABLE_MASK;
|
|
}
|
|
|
|
/* Note: spte must be a shadow-present leaf SPTE. */
|
|
static inline void check_spte_writable_invariants(u64 spte)
|
|
{
|
|
if (spte & shadow_mmu_writable_mask)
|
|
WARN_ONCE(!(spte & shadow_host_writable_mask),
|
|
KBUILD_MODNAME ": MMU-writable SPTE is not Host-writable: %llx",
|
|
spte);
|
|
else
|
|
WARN_ONCE(is_writable_pte(spte),
|
|
KBUILD_MODNAME ": Writable SPTE is not MMU-writable: %llx", spte);
|
|
}
|
|
|
|
static inline bool is_mmu_writable_spte(u64 spte)
|
|
{
|
|
return spte & shadow_mmu_writable_mask;
|
|
}
|
|
|
|
static inline u64 get_mmio_spte_generation(u64 spte)
|
|
{
|
|
u64 gen;
|
|
|
|
gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_SHIFT;
|
|
gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_SHIFT;
|
|
return gen;
|
|
}
|
|
|
|
bool spte_has_volatile_bits(u64 spte);
|
|
|
|
bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
|
|
const struct kvm_memory_slot *slot,
|
|
unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn,
|
|
u64 old_spte, bool prefetch, bool can_unsync,
|
|
bool host_writable, u64 *new_spte);
|
|
u64 make_huge_page_split_spte(struct kvm *kvm, u64 huge_spte,
|
|
union kvm_mmu_page_role role, int index);
|
|
u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled);
|
|
u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access);
|
|
u64 mark_spte_for_access_track(u64 spte);
|
|
|
|
/* Restore an acc-track PTE back to a regular PTE */
|
|
static inline u64 restore_acc_track_spte(u64 spte)
|
|
{
|
|
u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
|
|
& SHADOW_ACC_TRACK_SAVED_BITS_MASK;
|
|
|
|
spte &= ~shadow_acc_track_mask;
|
|
spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
|
|
SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
|
|
spte |= saved_bits;
|
|
|
|
return spte;
|
|
}
|
|
|
|
u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn);
|
|
|
|
void __init kvm_mmu_spte_module_init(void);
|
|
void kvm_mmu_reset_all_pte_masks(void);
|
|
|
|
#endif
|