linux/drivers/net/dsa
Vladimir Oltean c8b8a3c601 net: dsa: mt7530: permit port 5 to work without port 6 on MT7621 SoC
The MT7530 switch from the MT7621 SoC has 2 ports which can be set up as
internal: port 5 and 6. Arınç reports that the GMAC1 attached to port 5
receives corrupted frames, unless port 6 (attached to GMAC0) has been
brought up by the driver. This is true regardless of whether port 5 is
used as a user port or as a CPU port (carrying DSA tags).

Offline debugging (blind for me) which began in the linked thread showed
experimentally that the configuration done by the driver for port 6
contains a step which is needed by port 5 as well - the write to
CORE_GSWPLL_GRP2 (note that I've no idea as to what it does, apart from
the comment "Set core clock into 500Mhz"). Prints put by Arınç show that
the reset value of CORE_GSWPLL_GRP2 is RG_GSWPLL_POSDIV_500M(1) |
RG_GSWPLL_FBKDIV_500M(40) (0x128), both on the MCM MT7530 from the
MT7621 SoC, as well as on the standalone MT7530 from MT7623NI Bananapi
BPI-R2. Apparently, port 5 on the standalone MT7530 can work under both
values of the register, while on the MT7621 SoC it cannot.

The call path that triggers the register write is:

mt753x_phylink_mac_config() for port 6
-> mt753x_pad_setup()
   -> mt7530_pad_clk_setup()

so this fully explains the behavior noticed by Arınç, that bringing port
6 up is necessary.

The simplest fix for the problem is to extract the register writes which
are needed for both port 5 and 6 into a common mt7530_pll_setup()
function, which is called at mt7530_setup() time, immediately after
switch reset. We can argue that this mirrors the code layout introduced
in mt7531_setup() by commit 42bc4fafe3 ("net: mt7531: only do PLL once
after the reset"), in that the PLL setup has the exact same positioning,
and further work to consolidate the separate setup() functions is not
hindered.

Testing confirms that:

- the slight reordering of writes to MT7530_P6ECR and to
  CORE_GSWPLL_GRP1 / CORE_GSWPLL_GRP2 introduced by this change does not
  appear to cause problems for the operation of port 6 on MT7621 and on
  MT7623 (where port 5 also always worked)

- packets sent through port 5 are not corrupted anymore, regardless of
  whether port 6 is enabled by phylink or not (or even present in the
  device tree)

My algorithm for determining the Fixes: tag is as follows. Testing shows
that some logic from mt7530_pad_clk_setup() is needed even for port 5.
Prior to commit ca366d6c88 ("net: dsa: mt7530: Convert to PHYLINK
API"), a call did exist for all phy_is_pseudo_fixed_link() ports - so
port 5 included. That commit replaced it with a temporary "Port 5 is not
supported!" comment, and the following commit 38f790a805 ("net: dsa:
mt7530: Add support for port 5") replaced that comment with a
configuration procedure in mt7530_setup_port5() which was insufficient
for port 5 to work. I'm laying the blame on the patch that claimed
support for port 5, although one would have also needed the change from
commit c3b8e07909 ("net: dsa: mt7530: setup core clock even in TRGMII
mode") for the write to be performed completely independently from port
6's configuration.

Thanks go to Arınç for describing the problem, for debugging and for
testing.

Reported-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Link: https://lore.kernel.org/netdev/f297c2c4-6e7c-57ac-2394-f6025d309b9d@arinc9.com/
Fixes: 38f790a805 ("net: dsa: mt7530: Add support for port 5")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Simon Horman <simon.horman@corigine.com>
Link: https://lore.kernel.org/r/20230307155411.868573-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-03-08 23:14:28 -08:00
..
b53 net: dsa: modularize DSA_TAG_PROTO_NONE 2022-11-22 20:41:45 -08:00
hirschmann net: devlink: let the core report the driver name instead of the drivers 2022-11-30 21:49:38 -08:00
microchip net: dsa: microchip: enable EEE support 2023-02-13 11:12:31 +00:00
mv88e6xxx net: dsa: mv88e6xxx: Enable PTP receive for mv88e6390 2023-01-16 13:36:57 +00:00
ocelot net: dsa: ocelot_ext: remove unnecessary phylink.h include 2023-02-26 18:41:33 +00:00
qca net: dsa: qca8k: convert to regmap read/write API 2023-01-27 12:06:45 +00:00
realtek net: dsa: realtek: remove unnecessary set_drvdata() 2022-09-22 19:30:39 -07:00
sja1105 net: Remove C45 check in C22 only MDIO bus drivers 2023-01-20 18:12:45 -08:00
xrs700x net: dsa: xrs700x: Convert to i2c's .probe_new() 2022-11-23 12:50:06 -08:00
bcm_sf2_cfp.c net: dsa: introduce dsa_port_get_master() 2022-09-20 10:32:35 +02:00
bcm_sf2_regs.h net: dsa: bcm_sf2: refactor LED regs access 2021-12-30 17:28:32 -08:00
bcm_sf2.c net: dsa: bcm_sf2: remove unnecessary platform_set_drvdata() 2022-09-22 19:30:35 -07:00
bcm_sf2.h net: dsa: bcm_sf2: refactor LED regs access 2021-12-30 17:28:32 -08:00
dsa_loop_bdinfo.c
dsa_loop.c net: dsa: Fix possible memory leaks in dsa_loop_init() 2022-10-28 10:32:59 +01:00
dsa_loop.h
Kconfig net: dsa: mt7530: fix tristate and help description 2023-01-27 22:33:49 -08:00
lan9303_i2c.c net: dsa: lan9303: Convert to i2c's .probe_new() 2022-11-23 12:50:05 -08:00
lan9303_mdio.c net: dsa: lan9303: remove unnecessary dev_set_drvdata() 2022-09-22 19:30:36 -07:00
lan9303-core.c dsa: lan9303: Add flow ctrl in link_up 2023-01-20 08:53:13 +00:00
lan9303.h net: dsa: be compatible with masters which unregister on shutdown 2021-09-19 12:08:37 +01:00
lantiq_gswip.c net: dsa: lantiq_gswip: remove unnecessary platform_set_drvdata() 2022-09-22 19:30:36 -07:00
lantiq_pce.h
Makefile net: dsa: qca8k: move driver to qca dir 2022-07-15 11:57:13 +01:00
mt7530.c net: dsa: mt7530: permit port 5 to work without port 6 on MT7621 SoC 2023-03-08 23:14:28 -08:00
mt7530.h net: dsa: mt7530: Separate C22 and C45 MDIO bus transactions 2023-01-17 19:34:07 -08:00
mv88e6060.c net: dsa: mv88e6060: remove unnecessary dev_set_drvdata() 2022-09-22 19:30:37 -07:00
mv88e6060.h
rzn1_a5psw.c net: Remove C45 check in C22 only MDIO bus drivers 2023-01-20 18:12:45 -08:00
rzn1_a5psw.h net: dsa: rzn1-a5psw: add FDB support 2022-06-27 11:37:55 +01:00
vitesse-vsc73xx-core.c net: dsa: vsc73xxx: Get rid of duplicate of_node assignment 2021-12-03 14:13:02 +00:00
vitesse-vsc73xx-platform.c net: dsa: vitesse-vsc73xx: remove unnecessary set_drvdata() 2022-09-22 19:30:39 -07:00
vitesse-vsc73xx-spi.c net: dsa: vitesse-vsc73xx: remove unnecessary set_drvdata() 2022-09-22 19:30:39 -07:00
vitesse-vsc73xx.h net: dsa: vsc73xxx: Make vsc73xx_remove() return void 2021-11-15 13:15:07 +00:00