mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-05 01:54:09 +08:00
786a72d791
Lots of changes as usual, so I'm trying to be brief here. Most of the
new hardware support has the respective driver changes merged through
other trees or has had it available for a while, so this is where things
come together.
We get a DT descriptions for a couple of new SoCs, all of them variants
of other chips we already support, and usually coming with a new
evaluation board:
- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
- Qualcomm MDM9615 LTE baseband
- NXP imx6ull, the latest and smallest i.MX6 application processor variant
- Renesas RZ/G (r8a7743 and r8a7745) application processors
- Rockchip PX3, a variant of the rk3188 chip used in Android tablets
- Rockchip rk1108 single-core application processor
- ST stm32f746 Cortex-M7 based microcontroller
- TI DRA71x automotive processors
These are commercially available consumer platforms we now support:
- Motorola Droid 4 (xt894) mobile phone
- Rikomagic MK808 Android TV stick based on Rockchips rx3066
- Cloud Engines PogoPlug v3 based on OX820
- Various Broadcom based wireless devices:
- Netgear R8500 router
- Tenda AC9 router
- TP-LINK Archer C9 V1
- Luxul XAP-1510 Access point
- Turris Omnia open hardware router based on Armada 385
And a couple of new boards targeted at developers, makers
or industrial integration:
- Macnica Sodia development platform for Altera socfpga (Cyclone V)
- MicroZed board based on Xilinx Zynq FPGA platforms
- TOPEET itop/elite based on exynos4412
- WP8548 MangOH Open Hardware platform for IOT, based on
Qualcomm MDM9615
- NextThing CHIP Pro gadget
- NanoPi M1 development board
- AM571x-IDK industrial board based on TI AM5718
- i.MX6SX UDOO Neo
- Boundary Devices Nitrogen6_SOM2 (i.MX6)
- Engicam i.CoreM6
- Grinn i.MX6UL liteSOM/liteBoard
- Toradex Colibri iMX6 module
Other changes:
- added peripherals on renesas, davinci, stm32f429, uniphier, sti,
mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
mvebu, allwinner, broadcom, exynos, zynq
- Continued fixes for W=1 dtc warnings
- The old STiH415/416 SoC support gets removed, these never made it into
products and have served their purpose in the kernel as a template
for teh newer chips from ST
- The exynos4415 dtsi file is removed as nothing uses it.
- Intel PXA25x can now be booted using devicetree
Conflicts:
arch/arm/boot/dts/r8a*.dtsi: a node was added
the clk tree, keep both sides and watch out for git
dropping the required '};' at the end of each side.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAWFMZHGCrR//JCVInAQKQ6A/+Og42qy1rhL3cfHiSsT7e5giQNVSFY7Cm
Z06R83AEv6HDMTNzyiJr5udRGOhm40qIoe92fhVJSRF7F6o/GbCQ7YOyU4KdQELg
caqRCe1Nq6RT0RYU0m6xVyv/ox0JTNEaB+TcvD1x4pgUQNo9sSBfiXpTzOKhLhqs
zmsfpNpj8v188Iofoju3WtwN26riJ7P4QdYIaNaH4qNQgoQbMbQICDwnpSsNJY+x
MSlNrbtYqfz6vc5fqa0mtfhF6wIFxuRnTgSLi9skWZ2l/fkn4ljF3RhN1Z86TYPv
CYsqDu+DF0YNxFrht3BAK6WTe2PdCnMNLNnMhYC6NDQ8YG1tbwvXQFM1KVanRvxx
hXP4Nt2sZYiqA4v8joFPgp9gnyBMdhtJEtWSmHwCY0RFObySJR4I1GY7igh02HUJ
gxlmOYcmklzLiyXvfjdDvg0sCV1tBhaBKTLYxF7lVCzG2QaR22Le+p3o+SWm+e+V
Ruc9l/iwHaeasNnbAkDEiEyi1FobtuEeTSZnKaXfKX8WuKVZLJrCEm7WiRIsj0Ww
vJ9ABVft7PEv/Ov3fbKBWON4vxKTBBgHuEDcbIsp19w4BSH1WJf5bGXIm7QeA3Z9
aD+DtA5W5ExIjMQR2+qgz/BBIzVVVVvG8DEcdcCtc3JGRJll5PadShLdqKjVIerc
SpsxqCKoRCI=
=wJt3
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"Lots of changes as usual, so I'm trying to be brief here. Most of the
new hardware support has the respective driver changes merged through
other trees or has had it available for a while, so this is where
things come together.
We get a DT descriptions for a couple of new SoCs, all of them
variants of other chips we already support, and usually coming with a
new evaluation board:
- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
- Qualcomm MDM9615 LTE baseband
- NXP imx6ull, the latest and smallest i.MX6 application processor variant
- Renesas RZ/G (r8a7743 and r8a7745) application processors
- Rockchip PX3, a variant of the rk3188 chip used in Android tablets
- Rockchip rk1108 single-core application processor
- ST stm32f746 Cortex-M7 based microcontroller
- TI DRA71x automotive processors
These are commercially available consumer platforms we now support:
- Motorola Droid 4 (xt894) mobile phone
- Rikomagic MK808 Android TV stick based on Rockchips rx3066
- Cloud Engines PogoPlug v3 based on OX820
- Various Broadcom based wireless devices:
- Netgear R8500 router
- Tenda AC9 router
- TP-LINK Archer C9 V1
- Luxul XAP-1510 Access point
- Turris Omnia open hardware router based on Armada 385
And a couple of new boards targeted at developers, makers or
industrial integration:
- Macnica Sodia development platform for Altera socfpga (Cyclone V)
- MicroZed board based on Xilinx Zynq FPGA platforms
- TOPEET itop/elite based on exynos4412
- WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615
- NextThing CHIP Pro gadget
- NanoPi M1 development board
- AM571x-IDK industrial board based on TI AM5718
- i.MX6SX UDOO Neo
- Boundary Devices Nitrogen6_SOM2 (i.MX6)
- Engicam i.CoreM6
- Grinn i.MX6UL liteSOM/liteBoard
- Toradex Colibri iMX6 module
Other changes:
- added peripherals on renesas, davinci, stm32f429, uniphier, sti,
mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
mvebu, allwinner, broadcom, exynos, zynq
- Continued fixes for W=1 dtc warnings
- The old STiH415/416 SoC support gets removed, these never made it
into products and have served their purpose in the kernel as a
template for teh newer chips from ST
- The exynos4415 dtsi file is removed as nothing uses it.
- Intel PXA25x can now be booted using devicetree"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits)
arm: dts: zynq: Add MicroZed board support
ARM: dts: da850: enable high speed for mmc
ARM: dts: da850: Add node for pullup/pulldown pinconf
ARM: dts: da850: enable memctrl and mstpri nodes per board
ARM: dts: da850-lcdk: Add ethernet0 alias to DT
ARM: dts: artpec: add pcie support
ARM: dts: add support for Turris Omnia
devicetree: Add vendor prefix for CZ.NIC
ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node
ARM: dts: berlin2q-marvell-dmp: fix regulators' name
ARM: dts: Add xo to sdhc clock node on qcom platforms
ARM: dts: r8a7794: Add device node for PRR
ARM: dts: r8a7793: Add device node for PRR
ARM: dts: r8a7792: Add device node for PRR
ARM: dts: r8a7791: Add device node for PRR
ARM: dts: r8a7790: Add device node for PRR
ARM: dts: r8a7779: Add device node for PRR
ARM: dts: r8a73a4: Add device node for PRR
ARM: dts: sk-rzg1e: add Ether support
ARM: dts: sk-rzg1e: initial device tree
...
994 lines
27 KiB
Plaintext
994 lines
27 KiB
Plaintext
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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* Copyright 2016 Toradex AG
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/imx7d-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "imx7d-pinfunc.h"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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serial6 = &uart7;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clock-frequency = <792000000>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX7D_CLK_ARM>;
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};
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};
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ckil: clock-cki {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "ckil";
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};
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osc: clock-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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funnel@30041000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x30041000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ca_funnel_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel input ports */
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port@0 {
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reg = <0>;
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ca_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out_port>;
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};
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};
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/* funnel output port */
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port@2 {
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reg = <0>;
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ca_funnel_out_port0: endpoint {
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remote-endpoint = <&hugo_funnel_in_port0>;
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};
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};
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/* the other input ports are not connect to anything */
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};
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};
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etm@3007c000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x3007c000 0x1000>;
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cpu = <&cpu0>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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port {
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etm0_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port0>;
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};
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};
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};
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funnel@30083000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x30083000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel input ports */
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port@0 {
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reg = <0>;
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hugo_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&ca_funnel_out_port0>;
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};
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};
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port@1 {
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reg = <1>;
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hugo_funnel_in_port1: endpoint {
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slave-mode; /* M4 input */
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};
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};
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port@2 {
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reg = <0>;
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hugo_funnel_out_port0: endpoint {
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remote-endpoint = <&etf_in_port>;
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};
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};
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/* the other input ports are not connect to anything */
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};
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};
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etf@30084000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x30084000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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etf_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&hugo_funnel_out_port0>;
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};
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};
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port@1 {
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reg = <0>;
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etf_out_port: endpoint {
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remote-endpoint = <&replicator_in_port0>;
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};
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};
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};
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};
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etr@30086000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x30086000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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port {
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etr_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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tpiu@30087000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0x30087000 0x1000>;
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
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clock-names = "apb_pclk";
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port {
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tpiu_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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replicator {
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/*
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* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell"
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*/
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compatible = "arm,coresight-replicator";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etr_in_port>;
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};
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};
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/* replicator input port */
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port@2 {
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reg = <0>;
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replicator_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etf_out_port>;
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};
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};
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};
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};
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intc: interrupt-controller@31001000 {
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compatible = "arm,cortex-a7-gic";
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x31001000 0x1000>,
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<0x31002000 0x2000>,
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<0x31004000 0x2000>,
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<0x31006000 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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aips1: aips-bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30000000 0x400000>;
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ranges;
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gpio1: gpio@30200000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30200000 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
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};
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gpio2: gpio@30210000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30210000 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 13 32>;
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};
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gpio3: gpio@30220000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
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reg = <0x30220000 0x10000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&iomuxc 0 45 29>;
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};
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gpio4: gpio@30230000 {
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compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30230000 0x10000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 74 24>;
|
|
};
|
|
|
|
gpio5: gpio@30240000 {
|
|
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30240000 0x10000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 98 18>;
|
|
};
|
|
|
|
gpio6: gpio@30250000 {
|
|
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30250000 0x10000>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 116 23>;
|
|
};
|
|
|
|
gpio7: gpio@30260000 {
|
|
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
|
|
reg = <0x30260000 0x10000>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 139 16>;
|
|
};
|
|
|
|
wdog1: wdog@30280000 {
|
|
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30280000 0x10000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
|
|
};
|
|
|
|
wdog2: wdog@30290000 {
|
|
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
|
reg = <0x30290000 0x10000>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog3: wdog@302a0000 {
|
|
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
|
reg = <0x302a0000 0x10000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog4: wdog@302b0000 {
|
|
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
|
|
reg = <0x302b0000 0x10000>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
|
|
compatible = "fsl,imx7d-iomuxc-lpsr";
|
|
reg = <0x302c0000 0x10000>;
|
|
fsl,input-sel = <&iomuxc>;
|
|
};
|
|
|
|
gpt1: gpt@302d0000 {
|
|
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
|
reg = <0x302d0000 0x10000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_GPT1_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpt2: gpt@302e0000 {
|
|
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
|
reg = <0x302e0000 0x10000>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_GPT2_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt3: gpt@302f0000 {
|
|
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
|
reg = <0x302f0000 0x10000>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_GPT3_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt4: gpt@30300000 {
|
|
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
|
|
reg = <0x30300000 0x10000>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_GPT4_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc: iomuxc@30330000 {
|
|
compatible = "fsl,imx7d-iomuxc";
|
|
reg = <0x30330000 0x10000>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@30340000 {
|
|
compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
|
|
reg = <0x30340000 0x10000>;
|
|
};
|
|
|
|
ocotp: ocotp-ctrl@30350000 {
|
|
compatible = "syscon";
|
|
reg = <0x30350000 0x10000>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>;
|
|
status = "disabled";
|
|
};
|
|
|
|
anatop: anatop@30360000 {
|
|
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
|
|
"syscon", "simple-bus";
|
|
reg = <0x30360000 0x10000>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
reg_1p0d: regulator-vdd1p0d {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd1p0d";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
anatop-reg-offset = <0x210>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <8>;
|
|
anatop-min-voltage = <800000>;
|
|
anatop-max-voltage = <1200000>;
|
|
anatop-enable-bit = <31>;
|
|
};
|
|
};
|
|
|
|
snvs: snvs@30370000 {
|
|
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
|
reg = <0x30370000 0x10000>;
|
|
|
|
snvs_rtc: snvs-rtc-lp {
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
regmap = <&snvs>;
|
|
offset = <0x34>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
snvs_poweroff: snvs-poweroff {
|
|
compatible = "syscon-poweroff";
|
|
regmap = <&snvs>;
|
|
offset = <0x38>;
|
|
mask = <0x60>;
|
|
};
|
|
|
|
snvs_pwrkey: snvs-powerkey {
|
|
compatible = "fsl,sec-v4.0-pwrkey";
|
|
regmap = <&snvs>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
linux,keycode = <KEY_POWER>;
|
|
wakeup-source;
|
|
};
|
|
};
|
|
|
|
clks: ccm@30380000 {
|
|
compatible = "fsl,imx7d-ccm";
|
|
reg = <0x30380000 0x10000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
#clock-cells = <1>;
|
|
clocks = <&ckil>, <&osc>;
|
|
clock-names = "ckil", "osc";
|
|
};
|
|
|
|
src: src@30390000 {
|
|
compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
|
|
reg = <0x30390000 0x10000>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
aips2: aips-bus@30400000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x30400000 0x400000>;
|
|
ranges;
|
|
|
|
adc1: adc@30610000 {
|
|
compatible = "fsl,imx7d-adc";
|
|
reg = <0x30610000 0x10000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
|
|
clock-names = "adc";
|
|
status = "disabled";
|
|
};
|
|
|
|
adc2: adc@30620000 {
|
|
compatible = "fsl,imx7d-adc";
|
|
reg = <0x30620000 0x10000>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
|
|
clock-names = "adc";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi4: ecspi@30630000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30630000 0x10000>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
|
|
<&clks IMX7D_ECSPI4_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@30660000 {
|
|
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30660000 0x10000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
|
|
<&clks IMX7D_PWM1_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@30670000 {
|
|
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30670000 0x10000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
|
|
<&clks IMX7D_PWM2_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@30680000 {
|
|
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30680000 0x10000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
|
|
<&clks IMX7D_PWM3_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@30690000 {
|
|
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
|
|
reg = <0x30690000 0x10000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
|
|
<&clks IMX7D_PWM4_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lcdif: lcdif@30730000 {
|
|
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
|
|
reg = <0x30730000 0x10000>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
|
|
<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
|
|
clock-names = "pix", "axi";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
aips3: aips-bus@30800000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x30800000 0x400000>;
|
|
ranges;
|
|
|
|
ecspi1: ecspi@30820000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30820000 0x10000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
|
|
<&clks IMX7D_ECSPI1_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: ecspi@30830000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30830000 0x10000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
|
|
<&clks IMX7D_ECSPI2_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi3: ecspi@30840000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x30840000 0x10000>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
|
|
<&clks IMX7D_ECSPI3_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@30860000 {
|
|
compatible = "fsl,imx7d-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30860000 0x10000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_UART1_ROOT_CLK>,
|
|
<&clks IMX7D_UART1_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@30890000 {
|
|
compatible = "fsl,imx7d-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30890000 0x10000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_UART2_ROOT_CLK>,
|
|
<&clks IMX7D_UART2_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@30880000 {
|
|
compatible = "fsl,imx7d-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30880000 0x10000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_UART3_ROOT_CLK>,
|
|
<&clks IMX7D_UART3_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
sai1: sai@308a0000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
|
reg = <0x308a0000 0x10000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_SAI1_IPG_CLK>,
|
|
<&clks IMX7D_SAI1_ROOT_CLK>,
|
|
<&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dma-names = "rx", "tx";
|
|
dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai2: sai@308b0000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
|
reg = <0x308b0000 0x10000>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_SAI2_IPG_CLK>,
|
|
<&clks IMX7D_SAI2_ROOT_CLK>,
|
|
<&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dma-names = "rx", "tx";
|
|
dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai3: sai@308c0000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
|
|
reg = <0x308c0000 0x10000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_SAI3_IPG_CLK>,
|
|
<&clks IMX7D_SAI3_ROOT_CLK>,
|
|
<&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dma-names = "rx", "tx";
|
|
dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan1: can@30a00000 {
|
|
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
|
|
reg = <0x30a00000 0x10000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CAN1_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan2: can@30a10000 {
|
|
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
|
|
reg = <0x30a10000 0x10000>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CAN2_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@30a20000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a20000 0x10000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@30a30000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a30000 0x10000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@30a40000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a40000 0x10000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@30a50000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
|
|
reg = <0x30a50000 0x10000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@30a60000 {
|
|
compatible = "fsl,imx7d-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30a60000 0x10000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_UART4_ROOT_CLK>,
|
|
<&clks IMX7D_UART4_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@30a70000 {
|
|
compatible = "fsl,imx7d-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30a70000 0x10000>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_UART5_ROOT_CLK>,
|
|
<&clks IMX7D_UART5_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@30a80000 {
|
|
compatible = "fsl,imx7d-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30a80000 0x10000>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_UART6_ROOT_CLK>,
|
|
<&clks IMX7D_UART6_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@30a90000 {
|
|
compatible = "fsl,imx7d-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x30a90000 0x10000>;
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_UART7_ROOT_CLK>,
|
|
<&clks IMX7D_UART7_ROOT_CLK>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg1: usb@30b10000 {
|
|
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
|
reg = <0x30b10000 0x200>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
|
fsl,usbphy = <&usbphynop1>;
|
|
fsl,usbmisc = <&usbmisc1 0>;
|
|
phy-clkgate-delay-us = <400>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh: usb@30b30000 {
|
|
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
|
|
reg = <0x30b30000 0x200>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_USB_CTRL_CLK>;
|
|
fsl,usbphy = <&usbphynop3>;
|
|
fsl,usbmisc = <&usbmisc3 0>;
|
|
phy_type = "hsic";
|
|
dr_mode = "host";
|
|
phy-clkgate-delay-us = <400>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc1: usbmisc@30b10200 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
|
reg = <0x30b10200 0x200>;
|
|
};
|
|
|
|
usbmisc3: usbmisc@30b30200 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
|
|
reg = <0x30b30200 0x200>;
|
|
};
|
|
|
|
usbphynop1: usbphynop1 {
|
|
compatible = "usb-nop-xceiv";
|
|
clocks = <&clks IMX7D_USB_PHY1_CLK>;
|
|
clock-names = "main_clk";
|
|
};
|
|
|
|
usbphynop3: usbphynop3 {
|
|
compatible = "usb-nop-xceiv";
|
|
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
|
|
clock-names = "main_clk";
|
|
};
|
|
|
|
usdhc1: usdhc@30b40000 {
|
|
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
|
reg = <0x30b40000 0x10000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_USDHC1_ROOT_CLK>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: usdhc@30b50000 {
|
|
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
|
reg = <0x30b50000 0x10000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_USDHC2_ROOT_CLK>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: usdhc@30b60000 {
|
|
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
|
|
reg = <0x30b60000 0x10000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_CLK_DUMMY>,
|
|
<&clks IMX7D_USDHC3_ROOT_CLK>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma: sdma@30bd0000 {
|
|
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
|
|
reg = <0x30bd0000 0x10000>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_SDMA_CORE_CLK>,
|
|
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
|
};
|
|
|
|
fec1: ethernet@30be0000 {
|
|
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
|
|
reg = <0x30be0000 0x10000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
|
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
|
|
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
|
|
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
|
|
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
fsl,num-tx-queues=<3>;
|
|
fsl,num-rx-queues=<3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|