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f7d3586f2d
Fix misspelled "ti,x-plate-ohms" property name of TI TSC2046
touchscreen controller.
Fixes: d09e6beafa ("ARM: dts: imx7d-sdb: Add support for touchscreen")
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
646 lines
16 KiB
Plaintext
646 lines
16 KiB
Plaintext
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "imx7d.dtsi"
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/ {
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model = "Freescale i.MX7 SabreSD Board";
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compatible = "fsl,imx7d-sdb", "fsl,imx7d";
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memory {
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reg = <0x80000000 0x80000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg2_vbus: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_otg2_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_can2_3v3: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "can2-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
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};
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reg_vref_1v8: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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regulator-name = "vref-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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};
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&adc1 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&adc2 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&cpu0 {
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arm-supply = <&sw1a_reg>;
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};
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&ecspi3 {
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fsl,spi-num-chipselects = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
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status = "okay";
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tsc2046@0 {
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compatible = "ti,tsc2046";
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reg = <0>;
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spi-max-frequency = <1000000>;
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pinctrl-names ="default";
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pinctrl-0 = <&pinctrl_tsc2046_pendown>;
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interrupt-parent = <&gpio2>;
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interrupts = <29 0>;
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pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
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ti,x-min = /bits/ 16 <0>;
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ti,x-max = /bits/ 16 <0>;
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ti,y-min = /bits/ 16 <0>;
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ti,y-max = /bits/ 16 <0>;
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ti,pressure-max = /bits/ 16 <0>;
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ti,x-plate-ohms = /bits/ 16 <400>;
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wakeup-source;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze3000@08 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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codec: wm8960@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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clock-names = "mclk";
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wlf,shared-lrclk;
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};
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};
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&lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif>;
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display = <&display0>;
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status = "okay";
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display0: display {
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bits-per-pixel = <16>;
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bus-width = <24>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <9200000>;
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hactive = <480>;
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vactive = <272>;
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hfront-porch = <8>;
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hback-porch = <4>;
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hsync-len = <41>;
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vback-porch = <2>;
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vfront-porch = <4>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
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wakeup-source;
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keep-power-in-suspend;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
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bus-width = <8>;
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fsl,tuning-step = <2>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx7d-sdb {
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
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MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
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MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
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MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
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MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
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MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
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MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
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MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
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MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
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MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
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MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
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MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
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MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
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MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
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MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
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MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
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MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
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MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
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MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
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MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
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MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
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>;
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};
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pinctrl_lcdif: lcdifgrp {
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fsl,pins = <
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MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
|
|
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
|
|
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
|
|
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
|
|
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
|
|
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
|
|
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
|
|
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
|
|
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
|
|
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
|
|
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
|
|
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
|
|
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
|
|
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
|
|
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
|
|
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
|
|
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
|
|
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
|
|
MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
|
|
MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
|
|
MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
|
|
MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
|
|
MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
|
|
MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
|
|
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
|
|
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
|
|
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
|
|
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
|
|
MX7D_PAD_LCD_RESET__LCD_RESET 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x110b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_tsc2046_pendown: tsc2046_pendown {
|
|
fsl,pins = <
|
|
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
|
|
MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
|
|
MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
|
|
MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart6: uart6grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
|
|
MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
|
|
MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
|
|
MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
|
|
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
|
|
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
|
|
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
|
|
>;
|
|
};
|
|
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
|
|
>;
|
|
};
|
|
};
|
|
};
|