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The ARM RealView Evaluation Baseboards are basically these:
- The original ARMv5 EB board with an ARM926EJ-S, ARM1136 or
ARM1176 core tile here described in arm-realview-eb.dts
no matter which of these core tiles is being used. This
can be emulated by QEMU "realview-eb" machine, which by
default will have the ARM926EJ-S core tile.
- The same board with one of three MPCore Core tiles:
ARM11MPCore, not to be confused with the similar ARM
PB11MPCore ARM11MPCore test system. This exist in
two revisions:
- Revision A modeled in arm-realview-eb-11mp.dts
- Revision B modeled arm-realview-eb-11mp-revb.dts
Revision B can be emulated by the QEMU
"realview-eb-mpcore" machine, but to match the hardware
also the argument -smp cpus=4 must be passed so that
it has four CPU cores, like the hardware.
There is also evidently from the code in the kernel a
Cortex-A9 core tile for the EB, and this is modeled in
arm-realview-eb-a9mp.dts based on the kernel boardfile.
I have not found a user guide for this EB core tile on
the ARM website and it seems uncommon. It is however
included for completeness.
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
167 lines
3.8 KiB
Plaintext
167 lines
3.8 KiB
Plaintext
/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "arm-realview-eb.dtsi"
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/ {
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model = "ARM RealView Emulation Baseboard";
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compatible = "arm,realview-eb";
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arm,hbi = <0x140>;
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/*
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* This is the core tile with the CPU and GIC etc for the
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* ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
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* or PMU.
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*
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* To run this machine with QEMU, specify the following:
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* qemu-system-arm -M realview-eb
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* Unless specified, QEMU will emulate an ARM926EJ-S core tile.
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* Switches -cpu arm1136 or -cpu arm1176 emulates the other
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* core tiles.
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*/
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-eb-soc", "simple-bus";
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regmap = <&syscon>;
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ranges;
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intc: interrupt-controller@10040000 {
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compatible = "arm,pl390";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x10041000 0x1000>,
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<0x10040000 0x100>;
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};
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};
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};
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/*
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* This adapts all the peripherals to the interrupt routing
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* to the GIC on the core tile.
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*/
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ðernet {
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interrupt-parent = <&intc>;
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interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usb {
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interrupt-parent = <&intc>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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};
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&aaci {
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interrupt-parent = <&intc>;
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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&mmc {
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interrupt-parent = <&intc>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 18 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi0 {
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interrupt-parent = <&intc>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi1 {
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interrupt-parent = <&intc>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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&charlcd {
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interrupt-parent = <&intc>;
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interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial0 {
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interrupt-parent = <&intc>;
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interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial1 {
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interrupt-parent = <&intc>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial2 {
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interrupt-parent = <&intc>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial3 {
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interrupt-parent = <&intc>;
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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&ssp {
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interrupt-parent = <&intc>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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};
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&wdog {
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interrupt-parent = <&intc>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer01 {
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interrupt-parent = <&intc>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer23 {
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interrupt-parent = <&intc>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio0 {
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interrupt-parent = <&intc>;
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio1 {
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interrupt-parent = <&intc>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio2 {
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interrupt-parent = <&intc>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&rtc {
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interrupt-parent = <&intc>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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&clcd {
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interrupt-parent = <&intc>;
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interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
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};
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