Mark Rutland 2b523f170e atomics/riscv: Define atomic64_fetch_add_unless() ... As a step towards unifying the atomic/atomic64/atomic_long APIs, this patch converts the arch/riscv implementation of atomic64_add_unless() into an implementation of atomic64_fetch_add_unless(). A wrapper in <linux/atomic.h> will build atomic_add_unless() atop of this, provided it is given a preprocessor definition. No functional change is intended as a result of this patch. Acked-by Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Albert Ou <albert@sifive.com> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/lkml/20180621121321.4761-14-mark.rutland@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>		2018-06-21 14:25:24 +02:00
..
asm-offsets.h
asm.h	RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros	2017-11-30 10:01:10 -08:00
atomic.h	atomics/riscv: Define atomic64_fetch_add_unless()	2018-06-21 14:25:24 +02:00
barrier.h	riscv/barrier: Define __smp_{store_release,load_acquire}	2018-04-02 19:59:43 -07:00
bitops.h	RISC-V: __test_and_op_bit_ord should be strongly ordered	2017-11-28 14:04:05 -08:00
bug.h	RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros	2017-11-30 10:01:10 -08:00
cache.h
cacheflush.h	riscv: use NULL instead of a plain 0	2018-06-07 08:01:50 -07:00
cmpxchg.h	riscv/atomic: Strengthen implementations with fences	2018-04-02 19:59:44 -07:00
compat.h
csr.h	riscv: rename sptbr to satp	2018-01-30 19:16:12 -08:00
current.h
delay.h
dma-mapping.h	riscv: add swiotlb support	2018-05-19 08:46:26 +02:00
elf.h
fence.h	riscv/spinlock: Strengthen implementations with fences	2018-04-02 19:59:43 -07:00
ftrace.h	riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support	2018-04-02 19:59:13 -07:00
hwcap.h
io.h	riscv: remove CONFIG_MMU ifdefs	2018-01-07 15:14:39 -08:00
irq.h
irqflags.h	riscv: rename SR_* constants to match the spec	2018-01-07 15:14:39 -08:00
Kbuild	perf: riscv: preliminary RISC-V support	2018-06-04 14:02:01 -07:00
kprobes.h
linkage.h
mmu_context.h	riscv: inline set_pgdir into its only caller	2018-01-30 19:16:17 -08:00
mmu.h	RISC-V: Flush I$ when making a dirty page executable	2017-11-30 12:58:25 -08:00
module.h	RISC-V: Add section of GOT.PLT for kernel module	2018-04-02 20:00:54 -07:00
page.h
pci.h	PCI: remove PCI_DMA_BUS_IS_PHYS	2018-05-07 07:15:41 +02:00
perf_event.h	perf: riscv: preliminary RISC-V support	2018-06-04 14:02:01 -07:00
pgalloc.h
pgtable-32.h
pgtable-64.h
pgtable-bits.h	mm: introduce ARCH_HAS_PTE_SPECIAL	2018-06-07 17:34:35 -07:00
pgtable.h	riscv: remove CONFIG_MMU ifdefs	2018-01-07 15:14:39 -08:00
processor.h
ptrace.h	riscv: rename SR_* constants to match the spec	2018-01-07 15:14:39 -08:00
sbi.h
smp.h
spinlock_types.h
spinlock.h	riscv/spinlock: Strengthen implementations with fences	2018-04-02 19:59:43 -07:00
string.h
switch_to.h
syscall.h
thread_info.h	Construct init thread stack in the linker script rather than by union	2018-01-09 23:21:02 +00:00
timex.h	RISC-V: Use define for get_cycles like other architectures	2017-11-30 10:12:21 -08:00
tlb.h
tlbflush.h	riscv: use NULL instead of a plain 0	2018-06-07 08:01:50 -07:00
uaccess.h	riscv: split the declaration of __copy_user	2018-06-09 12:34:31 -07:00
unistd.h	riscv: remove unused __ARCH_HAVE_MMU define	2018-01-30 19:11:43 -08:00
vdso.h	RISC-V: Allow userspace to flush the instruction cache	2017-11-30 12:58:29 -08:00
word-at-a-time.h