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e7ccd8a49a
"make dtbs_check":
arch/arm/boot/dts/r8a7791-koelsch.dtb: apmu@e6152000: cpus:0: [6, 7] is too long
From schema: Documentation/devicetree/bindings/power/renesas,apmu.yaml
Correct the minimum and maximum number of CPUs controlled by a single
APMU instance.
Fixes: 39bd2b6a37 ("dt-bindings: Improve phandle-array schemas")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/9ece1a07bbcb95abc9d80e6a6ecc95806a294a11.1648645279.git.geert+renesas@glider.be
60 lines
1.6 KiB
YAML
60 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/power/renesas,apmu.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Renesas Advanced Power Management Unit
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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- Magnus Damm <magnus.damm@gmail.com>
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description:
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Renesas R-Car Gen2 and RZ/G1 SoCs utilize one or more APMU hardware units for
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CPU core power domain control including SMP boot and CPU Hotplug.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r8a7742-apmu # RZ/G1H
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- renesas,r8a7743-apmu # RZ/G1M
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- renesas,r8a7744-apmu # RZ/G1N
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- renesas,r8a7745-apmu # RZ/G1E
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- renesas,r8a77470-apmu # RZ/G1C
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- renesas,r8a7790-apmu # R-Car H2
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- renesas,r8a7791-apmu # R-Car M2-W
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- renesas,r8a7792-apmu # R-Car V2H
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- renesas,r8a7793-apmu # R-Car M2-N
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- renesas,r8a7794-apmu # R-Car E2
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- const: renesas,apmu
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reg:
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maxItems: 1
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cpus:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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minItems: 1
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maxItems: 4
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description: |
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Array of phandles pointing to CPU cores, which should match the order of
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CPU cores used by the WUPCR and PSTR registers in the Advanced Power
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Management Unit section of the device's datasheet.
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required:
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- compatible
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- reg
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- cpus
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additionalProperties: false
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examples:
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- |
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apmu@e6152000 {
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compatible = "renesas,r8a7791-apmu", "renesas,apmu";
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reg = <0xe6152000 0x188>;
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cpus = <&cpu0>, <&cpu1>;
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};
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