mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 23:14:31 +08:00
ceb694997e
This patch tidies up the code. I have run Linden (and verified with checkpatch) many part of the driver trying to reorganize some sections respecting the codying-style rules in the points where it was not done. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
220 lines
5.5 KiB
C
220 lines
5.5 KiB
C
/*******************************************************************************
|
|
Header File to describe the DMA descriptors.
|
|
Enhanced descriptors have been in case of DWMAC1000 Cores.
|
|
|
|
This program is free software; you can redistribute it and/or modify it
|
|
under the terms and conditions of the GNU General Public License,
|
|
version 2, as published by the Free Software Foundation.
|
|
|
|
This program is distributed in the hope it will be useful, but WITHOUT
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
more details.
|
|
|
|
You should have received a copy of the GNU General Public License along with
|
|
this program; if not, write to the Free Software Foundation, Inc.,
|
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
|
|
|
The full GNU General Public License is included in this distribution in
|
|
the file called "COPYING".
|
|
|
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
|
*******************************************************************************/
|
|
|
|
#ifndef __DESCS_H__
|
|
#define __DESCS_H__
|
|
|
|
/* Basic descriptor structure for normal and alternate descriptors */
|
|
struct dma_desc {
|
|
/* Receive descriptor */
|
|
union {
|
|
struct {
|
|
/* RDES0 */
|
|
u32 payload_csum_error:1;
|
|
u32 crc_error:1;
|
|
u32 dribbling:1;
|
|
u32 mii_error:1;
|
|
u32 receive_watchdog:1;
|
|
u32 frame_type:1;
|
|
u32 collision:1;
|
|
u32 ipc_csum_error:1;
|
|
u32 last_descriptor:1;
|
|
u32 first_descriptor:1;
|
|
u32 vlan_tag:1;
|
|
u32 overflow_error:1;
|
|
u32 length_error:1;
|
|
u32 sa_filter_fail:1;
|
|
u32 descriptor_error:1;
|
|
u32 error_summary:1;
|
|
u32 frame_length:14;
|
|
u32 da_filter_fail:1;
|
|
u32 own:1;
|
|
/* RDES1 */
|
|
u32 buffer1_size:11;
|
|
u32 buffer2_size:11;
|
|
u32 reserved1:2;
|
|
u32 second_address_chained:1;
|
|
u32 end_ring:1;
|
|
u32 reserved2:5;
|
|
u32 disable_ic:1;
|
|
|
|
} rx;
|
|
struct {
|
|
/* RDES0 */
|
|
u32 rx_mac_addr:1;
|
|
u32 crc_error:1;
|
|
u32 dribbling:1;
|
|
u32 error_gmii:1;
|
|
u32 receive_watchdog:1;
|
|
u32 frame_type:1;
|
|
u32 late_collision:1;
|
|
u32 ipc_csum_error:1;
|
|
u32 last_descriptor:1;
|
|
u32 first_descriptor:1;
|
|
u32 vlan_tag:1;
|
|
u32 overflow_error:1;
|
|
u32 length_error:1;
|
|
u32 sa_filter_fail:1;
|
|
u32 descriptor_error:1;
|
|
u32 error_summary:1;
|
|
u32 frame_length:14;
|
|
u32 da_filter_fail:1;
|
|
u32 own:1;
|
|
/* RDES1 */
|
|
u32 buffer1_size:13;
|
|
u32 reserved1:1;
|
|
u32 second_address_chained:1;
|
|
u32 end_ring:1;
|
|
u32 buffer2_size:13;
|
|
u32 reserved2:2;
|
|
u32 disable_ic:1;
|
|
} erx; /* -- enhanced -- */
|
|
|
|
/* Transmit descriptor */
|
|
struct {
|
|
/* TDES0 */
|
|
u32 deferred:1;
|
|
u32 underflow_error:1;
|
|
u32 excessive_deferral:1;
|
|
u32 collision_count:4;
|
|
u32 vlan_frame:1;
|
|
u32 excessive_collisions:1;
|
|
u32 late_collision:1;
|
|
u32 no_carrier:1;
|
|
u32 loss_carrier:1;
|
|
u32 payload_error:1;
|
|
u32 frame_flushed:1;
|
|
u32 jabber_timeout:1;
|
|
u32 error_summary:1;
|
|
u32 ip_header_error:1;
|
|
u32 time_stamp_status:1;
|
|
u32 reserved1:13;
|
|
u32 own:1;
|
|
/* TDES1 */
|
|
u32 buffer1_size:11;
|
|
u32 buffer2_size:11;
|
|
u32 time_stamp_enable:1;
|
|
u32 disable_padding:1;
|
|
u32 second_address_chained:1;
|
|
u32 end_ring:1;
|
|
u32 crc_disable:1;
|
|
u32 checksum_insertion:2;
|
|
u32 first_segment:1;
|
|
u32 last_segment:1;
|
|
u32 interrupt:1;
|
|
} tx;
|
|
struct {
|
|
/* TDES0 */
|
|
u32 deferred:1;
|
|
u32 underflow_error:1;
|
|
u32 excessive_deferral:1;
|
|
u32 collision_count:4;
|
|
u32 vlan_frame:1;
|
|
u32 excessive_collisions:1;
|
|
u32 late_collision:1;
|
|
u32 no_carrier:1;
|
|
u32 loss_carrier:1;
|
|
u32 payload_error:1;
|
|
u32 frame_flushed:1;
|
|
u32 jabber_timeout:1;
|
|
u32 error_summary:1;
|
|
u32 ip_header_error:1;
|
|
u32 time_stamp_status:1;
|
|
u32 reserved1:2;
|
|
u32 second_address_chained:1;
|
|
u32 end_ring:1;
|
|
u32 checksum_insertion:2;
|
|
u32 reserved2:1;
|
|
u32 time_stamp_enable:1;
|
|
u32 disable_padding:1;
|
|
u32 crc_disable:1;
|
|
u32 first_segment:1;
|
|
u32 last_segment:1;
|
|
u32 interrupt:1;
|
|
u32 own:1;
|
|
/* TDES1 */
|
|
u32 buffer1_size:13;
|
|
u32 reserved3:3;
|
|
u32 buffer2_size:13;
|
|
u32 reserved4:3;
|
|
} etx; /* -- enhanced -- */
|
|
} des01;
|
|
unsigned int des2;
|
|
unsigned int des3;
|
|
};
|
|
|
|
/* Extended descriptor structure (supported by new SYNP GMAC generations) */
|
|
struct dma_extended_desc {
|
|
struct dma_desc basic;
|
|
union {
|
|
struct {
|
|
u32 ip_payload_type:3;
|
|
u32 ip_hdr_err:1;
|
|
u32 ip_payload_err:1;
|
|
u32 ip_csum_bypassed:1;
|
|
u32 ipv4_pkt_rcvd:1;
|
|
u32 ipv6_pkt_rcvd:1;
|
|
u32 msg_type:4;
|
|
u32 ptp_frame_type:1;
|
|
u32 ptp_ver:1;
|
|
u32 timestamp_dropped:1;
|
|
u32 reserved:1;
|
|
u32 av_pkt_rcvd:1;
|
|
u32 av_tagged_pkt_rcvd:1;
|
|
u32 vlan_tag_priority_val:3;
|
|
u32 reserved3:3;
|
|
u32 l3_filter_match:1;
|
|
u32 l4_filter_match:1;
|
|
u32 l3_l4_filter_no_match:2;
|
|
u32 reserved4:4;
|
|
} erx;
|
|
struct {
|
|
u32 reserved;
|
|
} etx;
|
|
} des4;
|
|
unsigned int des5; /* Reserved */
|
|
unsigned int des6; /* Tx/Rx Timestamp Low */
|
|
unsigned int des7; /* Tx/Rx Timestamp High */
|
|
};
|
|
|
|
/* Transmit checksum insertion control */
|
|
enum tdes_csum_insertion {
|
|
cic_disabled = 0, /* Checksum Insertion Control */
|
|
cic_only_ip = 1, /* Only IP header */
|
|
/* IP header but pseudoheader is not calculated */
|
|
cic_no_pseudoheader = 2,
|
|
cic_full = 3, /* IP header and pseudoheader */
|
|
};
|
|
|
|
/* Extended RDES4 definitions */
|
|
#define RDES_EXT_NO_PTP 0
|
|
#define RDES_EXT_SYNC 0x1
|
|
#define RDES_EXT_FOLLOW_UP 0x2
|
|
#define RDES_EXT_DELAY_REQ 0x3
|
|
#define RDES_EXT_DELAY_RESP 0x4
|
|
#define RDES_EXT_PDELAY_REQ 0x5
|
|
#define RDES_EXT_PDELAY_RESP 0x6
|
|
#define RDES_EXT_PDELAY_FOLLOW_UP 0x7
|
|
|
|
#endif /* __DESCS_H__ */
|