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498574970f
* A handful of DT updates for the PolarFire SOC. * A fix to correct the handling of write-only mappings. * m{vetndor,arcd,imp}id is now in /proc/cpuinfo * The SiFive L2 cache controller support has been refactored to also support L3 caches. There's also a handful of fixes, cleanups and improvements throughout the tree. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmNJiegTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiaW+D/9nN7JMKD4KbED8MUgRVcs+TS4MQk5J QkjmAXme7w2H1+T5mxNWHk0QvEC6qMu2JQWHeott0ROYPkbXoNtuOOkzcsZhVaeb rjWH/WC5QhEeMPDc1qc0AmxVkOa937f2NkGtoEvhW6SMWvStHpefdOHo/ij106Re 7wxkcj0fjgn/zPmDltRbWSMyFZWJec5DvZ3AB4NYHnc2ycr8Z7HAG08rjZkdkIjQ zYGsCkUtrk4qShikKK3cSelW6hH1/FdM+bAo0rzt1frmTw1FLaFOsZZjOaVYekzi l0jxsb8FRBWyKBFqcagukjZwFy6D+7Q+masb0cXY03eZpEVrroA4bHiPkuZ22Ms/ 7ol/I5FvTyrj2R4zd70ziYVF3usO78t5HC4AIQmFl25TNcQdYQd8X28yh12iG6QN Pa0lh/EOr5idaT2+TErhzRepICnK1Nj9y0H5TZxYljLAhH9j0d/8+Iw88vzJnPga vek7unZ3BzkooLVIpfpkT8vC94MA0hoP849MVFQDtZgZhPMbjIkN91HrDiw9ktV2 SK9cuPndfrs5nW1WKu8F0cDziusbMHv4F51TPVRu/dFcIkspv+aLojAThgvcm42K 55LgvDgLjo7P3PUghiDXUoPZXvL19t5Bnq2/E47rlSTvvGssIu/onZO6BkxybAm6 BkHuchr8TGBWMg== =iCOr -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - DT updates for the PolarFire SOC - a fix to correct the handling of write-only mappings - m{vetndor,arcd,imp}id is now in /proc/cpuinfo - the SiFive L2 cache controller support has been refactored to also support L3 caches - misc fixes, cleanups and improvements throughout the tree * tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) MAINTAINERS: add RISC-V's patchwork RISC-V: Make port I/O string accessors actually work riscv: enable software resend of irqs RISC-V: Re-enable counter access from userspace riscv: vdso: fix NULL deference in vdso_join_timens() when vfork riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache riscv: check for kernel config option in t-head memory types errata riscv: use BIT() marco for cpufeature probing riscv: use BIT() macros in t-head errata init riscv: drop some idefs from CMO initialization riscv: cleanup svpbmt cpufeature probing riscv: Pass -mno-relax only on lld < 15.0.0 RISC-V: Avoid dereferening NULL regs in die() dt-bindings: riscv: add new riscv,isa strings for emulators ... |
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.. | ||
compat_vdso | ||
probes | ||
vdso | ||
.gitignore | ||
alternative.c | ||
asm-offsets.c | ||
cacheinfo.c | ||
compat_signal.c | ||
compat_syscall_table.c | ||
cpu_ops_sbi.c | ||
cpu_ops_spinwait.c | ||
cpu_ops.c | ||
cpu-hotplug.c | ||
cpu.c | ||
cpufeature.c | ||
crash_dump.c | ||
crash_save_regs.S | ||
efi-header.S | ||
efi.c | ||
elf_kexec.c | ||
entry.S | ||
fpu.S | ||
ftrace.c | ||
head.h | ||
head.S | ||
image-vars.h | ||
irq.c | ||
jump_label.c | ||
kexec_relocate.S | ||
kgdb.c | ||
machine_kexec_file.c | ||
machine_kexec.c | ||
Makefile | ||
mcount-dyn.S | ||
mcount.S | ||
module-sections.c | ||
module.c | ||
patch.c | ||
perf_callchain.c | ||
perf_regs.c | ||
process.c | ||
ptrace.c | ||
reset.c | ||
riscv_ksyms.c | ||
sbi.c | ||
setup.c | ||
signal.c | ||
smp.c | ||
smpboot.c | ||
soc.c | ||
stacktrace.c | ||
suspend_entry.S | ||
suspend.c | ||
sys_riscv.c | ||
syscall_table.c | ||
time.c | ||
trace_irq.c | ||
trace_irq.h | ||
traps_misaligned.c | ||
traps.c | ||
vdso.c | ||
vmlinux-xip.lds.S | ||
vmlinux.lds.S |