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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
72 lines
3.5 KiB
C
72 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Parallel I/O Controller (PIO) - System peripherals registers.
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*/
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#ifndef __PINCTRL_AT91_H
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#define __PINCTRL_AT91_H
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#define PIO_PER 0x00 /* Enable Register */
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#define PIO_PDR 0x04 /* Disable Register */
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#define PIO_PSR 0x08 /* Status Register */
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#define PIO_OER 0x10 /* Output Enable Register */
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#define PIO_ODR 0x14 /* Output Disable Register */
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#define PIO_OSR 0x18 /* Output Status Register */
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#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
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#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
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#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
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#define PIO_SODR 0x30 /* Set Output Data Register */
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#define PIO_CODR 0x34 /* Clear Output Data Register */
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#define PIO_ODSR 0x38 /* Output Data Status Register */
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#define PIO_PDSR 0x3c /* Pin Data Status Register */
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#define PIO_IER 0x40 /* Interrupt Enable Register */
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#define PIO_IDR 0x44 /* Interrupt Disable Register */
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#define PIO_IMR 0x48 /* Interrupt Mask Register */
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#define PIO_ISR 0x4c /* Interrupt Status Register */
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#define PIO_MDER 0x50 /* Multi-driver Enable Register */
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#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
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#define PIO_MDSR 0x58 /* Multi-driver Status Register */
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#define PIO_PUDR 0x60 /* Pull-up Disable Register */
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#define PIO_PUER 0x64 /* Pull-up Enable Register */
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#define PIO_PUSR 0x68 /* Pull-up Status Register */
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#define PIO_ASR 0x70 /* Peripheral A Select Register */
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#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
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#define PIO_BSR 0x74 /* Peripheral B Select Register */
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#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
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#define PIO_ABSR 0x78 /* AB Status Register */
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#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
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#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
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#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
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#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
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#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
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#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
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#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
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#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
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#define PIO_OWER 0xa0 /* Output Write Enable Register */
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#define PIO_OWDR 0xa4 /* Output Write Disable Register */
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#define PIO_OWSR 0xa8 /* Output Write Status Register */
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#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
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#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
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#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
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#define PIO_ESR 0xc0 /* Edge Select Register */
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#define PIO_LSR 0xc4 /* Level Select Register */
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#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
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#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
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#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
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#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
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#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
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#define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
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#define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
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#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
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#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
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#define SAM9X60_PIO_SLEWR 0x110 /* PIO Slew Rate Control Register */
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#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */
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#endif
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