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e7e7e0d7be
If the clock tree is not fully populated when the timer-sun5i init code
is called, attempts to get the clock rate for the timer would fail and
return 0.
Make the init code for both clock events and clocksource check the
returned clock rate and fail gracefully if the result is 0, instead of
causing a divide by 0 exception later on.
Fixes: 4a59058f0b
("clocksource/drivers/sun5i: Refactor the current code")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
376 lines
9.4 KiB
C
376 lines
9.4 KiB
C
/*
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* Allwinner SoCs hstimer driver.
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*
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* Copyright (C) 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_EN(val) BIT(val)
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#define TIMER_IRQ_ST_REG 0x04
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#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
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#define TIMER_CTL_ENABLE BIT(0)
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#define TIMER_CTL_RELOAD BIT(1)
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#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
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#define TIMER_CTL_ONESHOT BIT(7)
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#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
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#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
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#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
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#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
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#define TIMER_SYNC_TICKS 3
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struct sun5i_timer {
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void __iomem *base;
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struct clk *clk;
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struct notifier_block clk_rate_cb;
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u32 ticks_per_jiffy;
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};
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#define to_sun5i_timer(x) \
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container_of(x, struct sun5i_timer, clk_rate_cb)
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struct sun5i_timer_clksrc {
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struct sun5i_timer timer;
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struct clocksource clksrc;
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};
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#define to_sun5i_timer_clksrc(x) \
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container_of(x, struct sun5i_timer_clksrc, clksrc)
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struct sun5i_timer_clkevt {
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struct sun5i_timer timer;
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struct clock_event_device clkevt;
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};
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#define to_sun5i_timer_clkevt(x) \
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container_of(x, struct sun5i_timer_clkevt, clkevt)
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/*
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* When we disable a timer, we need to wait at least for 2 cycles of
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* the timer source clock. We will use for that the clocksource timer
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* that is already setup and runs at the same frequency than the other
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* timers, and we never will be disabled.
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*/
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static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
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{
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u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
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while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
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cpu_relax();
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}
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static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
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{
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u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
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writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
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sun5i_clkevt_sync(ce);
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}
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static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
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{
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writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
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}
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static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
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{
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u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
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if (periodic)
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val &= ~TIMER_CTL_ONESHOT;
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else
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val |= TIMER_CTL_ONESHOT;
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writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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ce->timer.base + TIMER_CTL_REG(timer));
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}
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static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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return 0;
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}
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static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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sun5i_clkevt_time_start(ce, 0, false);
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return 0;
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}
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static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
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sun5i_clkevt_time_start(ce, 0, true);
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return 0;
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}
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static int sun5i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *clkevt)
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{
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struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
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sun5i_clkevt_time_stop(ce, 0);
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sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
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sun5i_clkevt_time_start(ce, 0, false);
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return 0;
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}
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static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
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{
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struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;
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writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
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ce->clkevt.event_handler(&ce->clkevt);
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return IRQ_HANDLED;
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}
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static u64 sun5i_clksrc_read(struct clocksource *clksrc)
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{
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struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
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return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
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}
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static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct sun5i_timer *timer = to_sun5i_timer(nb);
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struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
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switch (event) {
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case PRE_RATE_CHANGE:
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clocksource_unregister(&cs->clksrc);
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break;
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case POST_RATE_CHANGE:
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clocksource_register_hz(&cs->clksrc, ndata->new_rate);
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break;
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default:
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break;
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}
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return NOTIFY_DONE;
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}
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static int __init sun5i_setup_clocksource(struct device_node *node,
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void __iomem *base,
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struct clk *clk, int irq)
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{
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struct sun5i_timer_clksrc *cs;
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unsigned long rate;
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int ret;
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cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clock\n");
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goto err_free;
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}
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rate = clk_get_rate(clk);
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if (!rate) {
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pr_err("Couldn't get parent clock rate\n");
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ret = -EINVAL;
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goto err_disable_clk;
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}
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cs->timer.base = base;
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cs->timer.clk = clk;
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cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
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cs->timer.clk_rate_cb.next = NULL;
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ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
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if (ret) {
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pr_err("Unable to register clock notifier.\n");
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goto err_disable_clk;
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}
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writel(~0, base + TIMER_INTVAL_LO_REG(1));
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writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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base + TIMER_CTL_REG(1));
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cs->clksrc.name = node->name;
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cs->clksrc.rating = 340;
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cs->clksrc.read = sun5i_clksrc_read;
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cs->clksrc.mask = CLOCKSOURCE_MASK(32);
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cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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ret = clocksource_register_hz(&cs->clksrc, rate);
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if (ret) {
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pr_err("Couldn't register clock source.\n");
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goto err_remove_notifier;
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}
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return 0;
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err_remove_notifier:
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clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
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err_disable_clk:
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clk_disable_unprepare(clk);
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err_free:
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kfree(cs);
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return ret;
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}
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static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct sun5i_timer *timer = to_sun5i_timer(nb);
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struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
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if (event == POST_RATE_CHANGE) {
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clockevents_update_freq(&ce->clkevt, ndata->new_rate);
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ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
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}
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return NOTIFY_DONE;
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}
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static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
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struct clk *clk, int irq)
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{
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struct sun5i_timer_clkevt *ce;
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unsigned long rate;
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int ret;
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u32 val;
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ce = kzalloc(sizeof(*ce), GFP_KERNEL);
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if (!ce)
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return -ENOMEM;
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clock\n");
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goto err_free;
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}
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rate = clk_get_rate(clk);
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if (!rate) {
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pr_err("Couldn't get parent clock rate\n");
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ret = -EINVAL;
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goto err_disable_clk;
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}
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ce->timer.base = base;
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ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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ce->timer.clk = clk;
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ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
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ce->timer.clk_rate_cb.next = NULL;
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ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
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if (ret) {
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pr_err("Unable to register clock notifier.\n");
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goto err_disable_clk;
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}
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ce->clkevt.name = node->name;
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ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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ce->clkevt.set_next_event = sun5i_clkevt_next_event;
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ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
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ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
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ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
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ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
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ce->clkevt.rating = 340;
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ce->clkevt.irq = irq;
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ce->clkevt.cpumask = cpu_possible_mask;
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/* Enable timer0 interrupt */
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val = readl(base + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
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clockevents_config_and_register(&ce->clkevt, rate,
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TIMER_SYNC_TICKS, 0xffffffff);
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ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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"sun5i_timer0", ce);
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if (ret) {
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pr_err("Unable to register interrupt\n");
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goto err_remove_notifier;
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}
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return 0;
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err_remove_notifier:
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clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
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err_disable_clk:
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clk_disable_unprepare(clk);
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err_free:
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kfree(ce);
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return ret;
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}
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static int __init sun5i_timer_init(struct device_node *node)
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{
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struct reset_control *rstc;
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void __iomem *timer_base;
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struct clk *clk;
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int irq, ret;
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timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(timer_base)) {
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pr_err("Can't map registers\n");
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return PTR_ERR(timer_base);
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_err("Can't parse IRQ\n");
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return -EINVAL;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock\n");
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return PTR_ERR(clk);
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}
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rstc = of_reset_control_get(node, NULL);
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if (!IS_ERR(rstc))
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reset_control_deassert(rstc);
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ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
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if (ret)
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return ret;
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return sun5i_setup_clockevent(node, timer_base, clk, irq);
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}
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TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
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sun5i_timer_init);
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TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
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sun5i_timer_init);
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