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https://mirrors.bfsu.edu.cn/git/linux.git
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a907047732
The most notable updates this time are for Qualcomm Snapdragon platforms. The Inline-Crypto-Engine gets a new DT binding and driver. A number of drivers now support additional Snapdragon variants, in particular the rsc, scm, geni, bwm, glink and socinfo, while the llcc (edac) and rpm drivers get notable functionality updates. Updates on other platforms include: - Various updates to the Mediatek mutex and mmsys drivers, including support for the Helio X10 SoC - Support for unidirectional mailbox channels in Arm SCMI firmware - Support for per cpu asynchronous notification in OP-TEE firmware - Minor updates for memory controller drivers. - Minor updates for Renesas, TI, Amlogic, Apple, Broadcom, Tegra, Allwinner, Versatile Express, Canaan, Microchip, Mediatek and i.MX SoC drivers, mainly updating the use of MODULE_LICENSE() macros and obsolete DT driver interfaces. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmRGmncACgkQYKtH/8kJ Uif6ghAAw1TiPTJzJLLCNx+txOVFB62WDglv3T1CufjfcWp0Eh0RJSCcsCOPV+/7 UHi4+X4nPAcudeOFMFtslCR8ExLRWY4j7t2ZYo/k+VI3jdB8Qkbr6NAQgAuRdLYX WZ1cV6o76B3bhO2HqSVNVZ8/3Z7OAYw4j9VDD/4AbW+l3GyentlQTjabpJNREvSS 5HzT3ZI33o7M8mM4uYmmEXVrg8sCupbRyL9S7jTiFXRLcfqujclhfezJ4UrJJv7b wxGf+e2YNMqKH6PiKYufzN1TYI2D0YQeB1m56Y9FsAKxgAyHh2xWpsHeyVnaw0jc KaKjRN/H3JDlW/VCMAjQOIShCZdAs02xHnEXxY6pKLMM6i8/FkzzNIxNQwXrx5KH zYESXVd6suOI0eCZT8zkKKLHRT5EJRaliUv5Z+Qp2BBe3vJVZD0JqSlZ7lOznplF lviwL6ydAMr2cfTgfMxbRiYQVDzncFkfnR3t55SC6rYjGt6QWjeS0dDbGHf4WVC4 FDbnST4JaBmi+frh55VooX7EpzIv9wa0/taayaChd9qvXnh22uqaqho1sPYKZ6BI OXduHQ3qojJhKKKK1VJKzN5Ef3OHLQLNrvcc1DsKILrrES4w4LX1C9dmyh2CLXLo q5cX6L1iB1Hx5tujalDYBsHBBmbiT/1tNM2S7pAGigiGy4KEc28= =r6jm -----END PGP SIGNATURE----- Merge tag 'soc-drivers-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "The most notable updates this time are for Qualcomm Snapdragon platforms. The Inline-Crypto-Engine gets a new DT binding and driver, and a number of drivers now support additional Snapdragon variants, in particular the rsc, scm, geni, bwm, glink and socinfo, while the llcc (edac) and rpm drivers get notable functionality updates. Updates on other platforms include: - Various updates to the Mediatek mutex and mmsys drivers, including support for the Helio X10 SoC - Support for unidirectional mailbox channels in Arm SCMI firmware - Support for per cpu asynchronous notification in OP-TEE firmware - Minor updates for memory controller drivers. - Minor updates for Renesas, TI, Amlogic, Apple, Broadcom, Tegra, Allwinner, Versatile Express, Canaan, Microchip, Mediatek and i.MX SoC drivers, mainly updating the use of MODULE_LICENSE() macros and obsolete DT driver interfaces" * tag 'soc-drivers-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) soc: ti: smartreflex: Simplify getting the opam_sr pointer bus: vexpress-config: Add explicit of_platform.h include soc: mediatek: Kconfig: Add MTK_CMDQ dependency to MTK_MMSYS memory: mtk-smi: mt8365: Add SMI Support dt-bindings: memory-controllers: mediatek,smi-larb: add mt8365 dt-bindings: memory-controllers: mediatek,smi-common: add mt8365 memory: tegra: read values from correct device dt-bindings: crypto: Add Qualcomm Inline Crypto Engine soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver dt-bindings: firmware: document Qualcomm QCM2290 SCM soc: qcom: rpmh-rsc: Support RSC v3 minor versions soc: qcom: smd-rpm: Use GFP_ATOMIC in write path soc/tegra: fuse: Remove nvmem root only access soc/tegra: cbb: tegra194: Use of_address_count() helper soc/tegra: cbb: Remove MODULE_LICENSE in non-modules ARM: tegra: Remove MODULE_LICENSE in non-modules soc/tegra: flowctrl: Use devm_platform_get_and_ioremap_resource() soc: tegra: cbb: Drop empty platform remove function firmware: arm_scmi: Add support for unidirectional mailbox channels dt-bindings: firmware: arm,scmi: Support mailboxes unidirectional channels ...
414 lines
9.8 KiB
C
414 lines
9.8 KiB
C
/*
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* EIM driver for Freescale's i.MX chips
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*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/regmap.h>
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struct imx_weim_devtype {
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unsigned int cs_count;
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unsigned int cs_regs_count;
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unsigned int cs_stride;
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unsigned int wcr_offset;
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unsigned int wcr_bcm;
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unsigned int wcr_cont_bclk;
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};
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static const struct imx_weim_devtype imx1_weim_devtype = {
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.cs_count = 6,
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.cs_regs_count = 2,
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.cs_stride = 0x08,
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};
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static const struct imx_weim_devtype imx27_weim_devtype = {
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.cs_count = 6,
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.cs_regs_count = 3,
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.cs_stride = 0x10,
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};
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static const struct imx_weim_devtype imx50_weim_devtype = {
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.cs_count = 4,
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.cs_regs_count = 6,
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.cs_stride = 0x18,
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.wcr_offset = 0x90,
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.wcr_bcm = BIT(0),
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.wcr_cont_bclk = BIT(3),
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};
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static const struct imx_weim_devtype imx51_weim_devtype = {
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.cs_count = 6,
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.cs_regs_count = 6,
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.cs_stride = 0x18,
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};
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#define MAX_CS_REGS_COUNT 6
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#define MAX_CS_COUNT 6
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#define OF_REG_SIZE 3
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struct cs_timing {
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bool is_applied;
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u32 regs[MAX_CS_REGS_COUNT];
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};
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struct cs_timing_state {
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struct cs_timing cs[MAX_CS_COUNT];
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};
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struct weim_priv {
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void __iomem *base;
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struct cs_timing_state timing_state;
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};
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static const struct of_device_id weim_id_table[] = {
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/* i.MX1/21 */
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{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
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/* i.MX25/27/31/35 */
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{ .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
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/* i.MX50/53/6Q */
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{ .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
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{ .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
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/* i.MX51 */
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{ .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
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{ }
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};
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MODULE_DEVICE_TABLE(of, weim_id_table);
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static int imx_weim_gpr_setup(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct of_range_parser parser;
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struct of_range range;
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struct regmap *gpr;
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u32 gprvals[4] = {
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05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */
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033, /* CS0(64M) CS1(64M) CS2(0M) CS3(0M) */
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0113, /* CS0(64M) CS1(32M) CS2(32M) CS3(0M) */
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01111, /* CS0(32M) CS1(32M) CS2(32M) CS3(32M) */
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};
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u32 gprval = 0;
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u32 val;
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int cs = 0;
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int i = 0;
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gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
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if (IS_ERR(gpr)) {
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dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
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return 0;
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}
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if (of_range_parser_init(&parser, np))
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goto err;
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for_each_of_range(&parser, &range) {
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cs = range.bus_addr >> 32;
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val = (range.size / SZ_32M) | 1;
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gprval |= val << cs * 3;
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i++;
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}
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if (i == 0 || i % 4)
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goto err;
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for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
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if (gprval == gprvals[i]) {
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/* Found it. Set up IOMUXC_GPR1[11:0] with it. */
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regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
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return 0;
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}
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}
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err:
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dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
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return -EINVAL;
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}
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/* Parse and set the timing for this device. */
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static int weim_timing_setup(struct device *dev, struct device_node *np,
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const struct imx_weim_devtype *devtype)
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{
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u32 cs_idx, value[MAX_CS_REGS_COUNT];
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int i, ret;
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int reg_idx, num_regs;
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struct cs_timing *cst;
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struct weim_priv *priv;
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struct cs_timing_state *ts;
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void __iomem *base;
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if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
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return -EINVAL;
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if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
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return -EINVAL;
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priv = dev_get_drvdata(dev);
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base = priv->base;
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ts = &priv->timing_state;
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ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
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value, devtype->cs_regs_count);
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if (ret)
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return ret;
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/*
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* the child node's "reg" property may contain multiple address ranges,
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* extract the chip select for each.
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*/
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num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
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if (num_regs < 0)
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return num_regs;
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if (!num_regs)
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return -EINVAL;
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for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
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/* get the CS index from this child node's "reg" property. */
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ret = of_property_read_u32_index(np, "reg",
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reg_idx * OF_REG_SIZE, &cs_idx);
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if (ret)
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break;
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if (cs_idx >= devtype->cs_count)
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return -EINVAL;
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/* prevent re-configuring a CS that's already been configured */
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cst = &ts->cs[cs_idx];
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if (cst->is_applied && memcmp(value, cst->regs,
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devtype->cs_regs_count * sizeof(u32))) {
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dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
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return -EINVAL;
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}
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/* set the timing for WEIM */
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for (i = 0; i < devtype->cs_regs_count; i++)
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writel(value[i],
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base + cs_idx * devtype->cs_stride + i * 4);
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if (!cst->is_applied) {
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cst->is_applied = true;
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memcpy(cst->regs, value,
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devtype->cs_regs_count * sizeof(u32));
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}
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}
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return 0;
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}
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static int weim_parse_dt(struct platform_device *pdev)
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{
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const struct of_device_id *of_id = of_match_device(weim_id_table,
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&pdev->dev);
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const struct imx_weim_devtype *devtype = of_id->data;
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int ret = 0, have_child = 0;
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struct device_node *child;
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struct weim_priv *priv;
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void __iomem *base;
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u32 reg;
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if (devtype == &imx50_weim_devtype) {
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ret = imx_weim_gpr_setup(pdev);
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if (ret)
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return ret;
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}
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priv = dev_get_drvdata(&pdev->dev);
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base = priv->base;
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if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
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if (devtype->wcr_bcm) {
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reg = readl(base + devtype->wcr_offset);
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reg |= devtype->wcr_bcm;
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if (of_property_read_bool(pdev->dev.of_node,
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"fsl,continuous-burst-clk")) {
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if (devtype->wcr_cont_bclk) {
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reg |= devtype->wcr_cont_bclk;
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} else {
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dev_err(&pdev->dev,
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"continuous burst clk not supported.\n");
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return -EINVAL;
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}
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}
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writel(reg, base + devtype->wcr_offset);
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} else {
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dev_err(&pdev->dev, "burst clk mode not supported.\n");
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return -EINVAL;
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}
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}
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for_each_available_child_of_node(pdev->dev.of_node, child) {
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ret = weim_timing_setup(&pdev->dev, child, devtype);
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if (ret)
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dev_warn(&pdev->dev, "%pOF set timing failed.\n",
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child);
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else
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have_child = 1;
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}
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if (have_child)
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ret = of_platform_default_populate(pdev->dev.of_node,
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NULL, &pdev->dev);
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if (ret)
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dev_err(&pdev->dev, "%pOF fail to create devices.\n",
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pdev->dev.of_node);
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return ret;
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}
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static int weim_probe(struct platform_device *pdev)
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{
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struct weim_priv *priv;
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struct clk *clk;
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void __iomem *base;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* get the resource */
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base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(base))
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return PTR_ERR(base);
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priv->base = base;
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dev_set_drvdata(&pdev->dev, priv);
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/* get the clock */
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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/* parse the device node */
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ret = weim_parse_dt(pdev);
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if (ret)
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clk_disable_unprepare(clk);
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else
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dev_info(&pdev->dev, "Driver registered.\n");
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return ret;
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}
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#if IS_ENABLED(CONFIG_OF_DYNAMIC)
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static int of_weim_notify(struct notifier_block *nb, unsigned long action,
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void *arg)
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{
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const struct imx_weim_devtype *devtype;
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struct of_reconfig_data *rd = arg;
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const struct of_device_id *of_id;
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struct platform_device *pdev;
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int ret = NOTIFY_OK;
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switch (of_reconfig_get_state_change(action, rd)) {
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case OF_RECONFIG_CHANGE_ADD:
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of_id = of_match_node(weim_id_table, rd->dn->parent);
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if (!of_id)
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return NOTIFY_OK; /* not for us */
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devtype = of_id->data;
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pdev = of_find_device_by_node(rd->dn->parent);
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if (!pdev) {
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pr_err("%s: could not find platform device for '%pOF'\n",
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__func__, rd->dn->parent);
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return notifier_from_errno(-EINVAL);
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}
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if (weim_timing_setup(&pdev->dev, rd->dn, devtype))
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dev_warn(&pdev->dev,
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"Failed to setup timing for '%pOF'\n", rd->dn);
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if (!of_node_check_flag(rd->dn, OF_POPULATED)) {
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/*
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* Clear the flag before adding the device so that
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* fw_devlink doesn't skip adding consumers to this
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* device.
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*/
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rd->dn->fwnode.flags &= ~FWNODE_FLAG_NOT_DEVICE;
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if (!of_platform_device_create(rd->dn, NULL, &pdev->dev)) {
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dev_err(&pdev->dev,
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"Failed to create child device '%pOF'\n",
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rd->dn);
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ret = notifier_from_errno(-EINVAL);
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}
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}
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platform_device_put(pdev);
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break;
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case OF_RECONFIG_CHANGE_REMOVE:
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if (!of_node_check_flag(rd->dn, OF_POPULATED))
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return NOTIFY_OK; /* device already destroyed */
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of_id = of_match_node(weim_id_table, rd->dn->parent);
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if (!of_id)
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return NOTIFY_OK; /* not for us */
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pdev = of_find_device_by_node(rd->dn);
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if (!pdev) {
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pr_err("Could not find platform device for '%pOF'\n",
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rd->dn);
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ret = notifier_from_errno(-EINVAL);
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} else {
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of_platform_device_destroy(&pdev->dev, NULL);
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platform_device_put(pdev);
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}
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break;
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default:
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break;
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}
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return ret;
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}
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static struct notifier_block weim_of_notifier = {
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.notifier_call = of_weim_notify,
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};
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#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */
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static struct platform_driver weim_driver = {
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.driver = {
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.name = "imx-weim",
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.of_match_table = weim_id_table,
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},
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.probe = weim_probe,
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};
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static int __init weim_init(void)
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{
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#if IS_ENABLED(CONFIG_OF_DYNAMIC)
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WARN_ON(of_reconfig_notifier_register(&weim_of_notifier));
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#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */
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return platform_driver_register(&weim_driver);
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}
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module_init(weim_init);
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static void __exit weim_exit(void)
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{
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#if IS_ENABLED(CONFIG_OF_DYNAMIC)
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of_reconfig_notifier_unregister(&weim_of_notifier);
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#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */
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return platform_driver_unregister(&weim_driver);
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}
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module_exit(weim_exit);
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MODULE_AUTHOR("Freescale Semiconductor Inc.");
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MODULE_DESCRIPTION("i.MX EIM Controller Driver");
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MODULE_LICENSE("GPL");
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