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2eb5af44b1
This platform has not been converted to 'struct irq_data' when the big pile was done and fails to compile nowadays. Tested on a JayPC-Tablet. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Alexey Charkov <alchark@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
181 lines
4.5 KiB
C
181 lines
4.5 KiB
C
/*
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* arch/arm/mach-vt8500/irq.c
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*
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include "devices.h"
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#define VT8500_IC_DCTR 0x40 /* Destination control
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register, 64*u8 */
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#define VT8500_INT_ENABLE (1 << 3)
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#define VT8500_TRIGGER_HIGH (0 << 4)
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#define VT8500_TRIGGER_RISING (1 << 4)
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#define VT8500_TRIGGER_FALLING (2 << 4)
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#define VT8500_EDGE ( VT8500_TRIGGER_RISING \
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| VT8500_TRIGGER_FALLING)
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#define VT8500_IC_STATUS 0x80 /* Interrupt status, 2*u32 */
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static void __iomem *ic_regbase;
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static void __iomem *sic_regbase;
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static void vt8500_irq_mask(struct irq_data *d)
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{
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void __iomem *base = ic_regbase;
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unsigned irq = d->irq;
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u8 edge;
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if (irq >= 64) {
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base = sic_regbase;
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irq -= 64;
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}
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edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
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if (edge) {
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void __iomem *stat_reg = base + VT8500_IC_STATUS
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+ (irq < 32 ? 0 : 4);
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unsigned status = readl(stat_reg);
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status |= (1 << (irq & 0x1f));
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writel(status, stat_reg);
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} else {
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u8 dctr = readb(base + VT8500_IC_DCTR + irq);
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dctr &= ~VT8500_INT_ENABLE;
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writeb(dctr, base + VT8500_IC_DCTR + irq);
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}
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}
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static void vt8500_irq_unmask(struct irq_data *d)
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{
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void __iomem *base = ic_regbase;
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unsigned irq = d->irq;
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u8 dctr;
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if (irq >= 64) {
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base = sic_regbase;
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irq -= 64;
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}
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dctr = readb(base + VT8500_IC_DCTR + irq);
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dctr |= VT8500_INT_ENABLE;
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writeb(dctr, base + VT8500_IC_DCTR + irq);
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}
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static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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void __iomem *base = ic_regbase;
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unsigned irq = d->irq;
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unsigned orig_irq = irq;
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u8 dctr;
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if (irq >= 64) {
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base = sic_regbase;
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irq -= 64;
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}
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dctr = readb(base + VT8500_IC_DCTR + irq);
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dctr &= ~VT8500_EDGE;
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switch (flow_type) {
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case IRQF_TRIGGER_LOW:
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return -EINVAL;
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case IRQF_TRIGGER_HIGH:
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dctr |= VT8500_TRIGGER_HIGH;
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__irq_set_handler_locked(orig_irq, handle_level_irq);
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break;
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case IRQF_TRIGGER_FALLING:
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dctr |= VT8500_TRIGGER_FALLING;
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__irq_set_handler_locked(orig_irq, handle_edge_irq);
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break;
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case IRQF_TRIGGER_RISING:
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dctr |= VT8500_TRIGGER_RISING;
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__irq_set_handler_locked(orig_irq, handle_edge_irq);
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break;
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}
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writeb(dctr, base + VT8500_IC_DCTR + irq);
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return 0;
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}
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static struct irq_chip vt8500_irq_chip = {
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.name = "vt8500",
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.irq_ack = vt8500_irq_mask,
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.irq_mask = vt8500_irq_mask,
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.irq_unmask = vt8500_irq_unmask,
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.irq_set_type = vt8500_irq_set_type,
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};
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void __init vt8500_init_irq(void)
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{
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unsigned int i;
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ic_regbase = ioremap(wmt_ic_base, SZ_64K);
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if (ic_regbase) {
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/* Enable rotating priority for IRQ */
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writel((1 << 6), ic_regbase + 0x20);
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writel(0, ic_regbase + 0x24);
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for (i = 0; i < wmt_nr_irqs; i++) {
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/* Disable all interrupts and route them to IRQ */
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writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
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irq_set_chip_and_handler(i, &vt8500_irq_chip,
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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} else {
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printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
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}
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}
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void __init wm8505_init_irq(void)
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{
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unsigned int i;
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ic_regbase = ioremap(wmt_ic_base, SZ_64K);
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sic_regbase = ioremap(wmt_sic_base, SZ_64K);
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if (ic_regbase && sic_regbase) {
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/* Enable rotating priority for IRQ */
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writel((1 << 6), ic_regbase + 0x20);
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writel(0, ic_regbase + 0x24);
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writel((1 << 6), sic_regbase + 0x20);
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writel(0, sic_regbase + 0x24);
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for (i = 0; i < wmt_nr_irqs; i++) {
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/* Disable all interrupts and route them to IRQ */
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if (i < 64)
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writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
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else
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writeb(0x00, sic_regbase + VT8500_IC_DCTR
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+ i - 64);
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irq_set_chip_and_handler(i, &vt8500_irq_chip,
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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} else {
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printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
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}
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}
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