.. |
clk-agilex.c
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clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
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2020-06-19 19:27:33 -07:00 |
clk-gate-a10.c
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
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2019-05-30 11:29:52 -07:00 |
clk-gate-s10.c
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clk: socfpga: stratix10: use new parent data scheme
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2020-05-26 19:13:05 -07:00 |
clk-gate.c
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clk: socfpga: deindent code to proper indentation
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2019-08-16 10:20:07 -07:00 |
clk-periph-a10.c
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clk: socfpga: Don't reference clk_init_data after registration
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2019-08-16 10:20:07 -07:00 |
clk-periph-s10.c
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clk: socfpga: stratix10: use new parent data scheme
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2020-05-26 19:13:05 -07:00 |
clk-periph.c
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
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2019-05-30 11:26:37 -07:00 |
clk-pll-a10.c
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clk: socfpga: add const to _ops data structures
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2020-05-26 19:13:05 -07:00 |
clk-pll-s10.c
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clk: socfpga: agilex: add clock driver for the Agilex platform
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2020-05-26 19:13:05 -07:00 |
clk-pll.c
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clk: socfpga: add const to _ops data structures
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2020-05-26 19:13:05 -07:00 |
clk-s10.c
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clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk
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2020-09-22 12:54:41 -07:00 |
clk.c
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13
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2019-05-21 11:28:45 +02:00 |
clk.h
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288
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2019-06-05 17:36:37 +02:00 |
Makefile
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clk: socfpga: agilex: add clock driver for the Agilex platform
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2020-05-26 19:13:05 -07:00 |
stratix10-clk.h
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clk: socfpga: agilex: add clock driver for the Agilex platform
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2020-05-26 19:13:05 -07:00 |