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a255e9c869
Looks like when we converted everything over to Nvidia's class headers,
we mistakenly included the nvif/push507b.h instead of nvif/pushc37b.h,
which resulted in breaking CRC reporting for volta+:
nouveau 0000:1f:00.0: disp: chid 0 stat 10003361 reason 3
[RESERVED_METHOD] mthd 0d84 data 00000000 code 00000000
nouveau 0000:1f:00.0: disp: chid 0 stat 10003360 reason 3
[RESERVED_METHOD] mthd 0d80 data 00000000 code 00000000
nouveau 0000:1f:00.0: DRM: CRC notifier ctx for head 3 not finished
after 50ms
So, fix that.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Fixes: c4b27bc868
("drm/nouveau/kms/nv50-: convert core crc_set_src() to new push macros")
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
155 lines
3.9 KiB
C
155 lines
3.9 KiB
C
// SPDX-License-Identifier: MIT
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#include <drm/drm_crtc.h>
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#include "crc.h"
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#include "core.h"
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#include "disp.h"
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#include "head.h"
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#include <nvif/pushc37b.h>
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#include <nvhw/class/clc37d.h>
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#define CRCC37D_MAX_ENTRIES 2047
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struct crcc37d_notifier {
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u32 status;
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/* reserved */
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u32 :32;
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u32 :32;
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u32 :32;
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u32 :32;
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u32 :32;
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u32 :32;
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u32 :32;
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struct crcc37d_entry {
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u32 status[2];
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u32 :32; /* reserved */
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u32 compositor_crc;
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u32 rg_crc;
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u32 output_crc[2];
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u32 :32; /* reserved */
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} entries[CRCC37D_MAX_ENTRIES];
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} __packed;
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static int
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crcc37d_set_src(struct nv50_head *head, int or,
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enum nv50_crc_source_type source,
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struct nv50_crc_notifier_ctx *ctx, u32 wndw)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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u32 crc_args = NVVAL(NVC37D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, wndw) |
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NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
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NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |
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NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE);
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int ret;
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switch (source) {
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case NV50_CRC_SOURCE_TYPE_SOR:
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crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or));
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break;
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case NV50_CRC_SOURCE_TYPE_PIOR:
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crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, PIOR(or));
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break;
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case NV50_CRC_SOURCE_TYPE_SF:
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crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF);
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break;
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default:
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break;
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}
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if ((ret = PUSH_WAIT(push, 4)))
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return ret;
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if (source) {
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
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PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args);
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} else {
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PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0);
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
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}
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return 0;
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}
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static int
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crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 2)))
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return ret;
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PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
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return 0;
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}
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static u32 crcc37d_get_entry(struct nv50_head *head,
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struct nv50_crc_notifier_ctx *ctx,
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enum nv50_crc_source source, int idx)
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{
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struct crcc37d_notifier __iomem *notifier = ctx->mem.object.map.ptr;
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struct crcc37d_entry __iomem *entry = ¬ifier->entries[idx];
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u32 __iomem *crc_addr;
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if (source == NV50_CRC_SOURCE_RG)
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crc_addr = &entry->rg_crc;
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else
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crc_addr = &entry->output_crc[0];
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return ioread32_native(crc_addr);
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}
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static bool crcc37d_ctx_finished(struct nv50_head *head,
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struct nv50_crc_notifier_ctx *ctx)
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{
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struct nouveau_drm *drm = nouveau_drm(head->base.base.dev);
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struct crcc37d_notifier __iomem *notifier = ctx->mem.object.map.ptr;
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const u32 status = ioread32_native(¬ifier->status);
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const u32 overflow = status & 0x0000007e;
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if (!(status & 0x00000001))
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return false;
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if (overflow) {
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const char *engine = NULL;
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switch (overflow) {
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case 0x00000004: engine = "Front End"; break;
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case 0x00000008: engine = "Compositor"; break;
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case 0x00000010: engine = "RG"; break;
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case 0x00000020: engine = "CRC output 1"; break;
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case 0x00000040: engine = "CRC output 2"; break;
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}
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if (engine)
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NV_ERROR(drm,
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"CRC notifier context for head %d overflowed on %s: %x\n",
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head->base.index, engine, status);
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else
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NV_ERROR(drm,
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"CRC notifier context for head %d overflowed: %x\n",
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head->base.index, status);
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}
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NV_DEBUG(drm, "Head %d CRC context status: %x\n",
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head->base.index, status);
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return true;
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}
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const struct nv50_crc_func crcc37d = {
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.set_src = crcc37d_set_src,
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.set_ctx = crcc37d_set_ctx,
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.get_entry = crcc37d_get_entry,
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.ctx_finished = crcc37d_ctx_finished,
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.flip_threshold = CRCC37D_MAX_ENTRIES - 30,
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.num_entries = CRCC37D_MAX_ENTRIES,
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.notifier_len = sizeof(struct crcc37d_notifier),
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};
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