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linux/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
kyrie wu 6611830fa3 dt-bindings: mediatek: Add mediatek, mt8195-jpgenc compatible
Add mediatek,mt8195-jpgenc compatible to binding document.

Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
Signed-off-by: irui wang <irui.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
2022-09-30 16:39:28 +02:00

148 lines
4.0 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Encoder
maintainers:
- kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
description:
MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
properties:
compatible:
const: mediatek,mt8195-jpgenc
power-domains:
maxItems: 1
iommus:
maxItems: 4
description:
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
# Required child node:
patternProperties:
"^jpgenc@[0-9a-f]+$":
type: object
description:
The jpeg encoder hardware device node which should be added as subnodes to
the main jpeg node.
properties:
compatible:
const: mediatek,mt8195-jpgenc-hw
reg:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description:
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: jpgenc
power-domains:
maxItems: 1
required:
- compatible
- reg
- iommus
- interrupts
- clocks
- clock-names
- power-domains
additionalProperties: false
required:
- compatible
- power-domains
- iommus
- dma-ranges
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
jpgenc-master {
compatible = "mediatek,mt8195-jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
jpgenc@1a030000 {
compatible = "mediatek,mt8195-jpgenc-hw";
reg = <0 0x1a030000 0 0x10000>;
iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
<&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGENC>;
clock-names = "jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
};
jpgenc@1b030000 {
compatible = "mediatek,mt8195-jpgenc-hw";
reg = <0 0x1b030000 0 0x10000>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
clock-names = "jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
};
};