mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-23 19:14:30 +08:00
a1f65e64c6
Document dt-bindings for Rockchip RV1126 clock controller. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20220915163947.1922183-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
63 lines
1.3 KiB
YAML
63 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Rockchip RV1126 Clock and Reset Unit
|
|
|
|
maintainers:
|
|
- Jagan Teki <jagan@edgeble.ai>
|
|
- Finley Xiao <finley.xiao@rock-chips.com>
|
|
- Heiko Stuebner <heiko@sntech.de>
|
|
|
|
description:
|
|
The RV1126 clock controller generates the clock and also implements a
|
|
reset controller for SoC peripherals.
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- rockchip,rv1126-cru
|
|
- rockchip,rv1126-pmucru
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
"#clock-cells":
|
|
const: 1
|
|
|
|
"#reset-cells":
|
|
const: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
clock-names:
|
|
const: xin24m
|
|
|
|
rockchip,grf:
|
|
$ref: /schemas/types.yaml#/definitions/phandle
|
|
description:
|
|
Phandle to the syscon managing the "general register files" (GRF),
|
|
if missing pll rates are not changeable, due to the missing pll
|
|
lock status.
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- "#clock-cells"
|
|
- "#reset-cells"
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
cru: clock-controller@ff490000 {
|
|
compatible = "rockchip,rv1126-cru";
|
|
reg = <0xff490000 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|