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The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
24 lines
722 B
Plaintext
24 lines
722 B
Plaintext
* Core Divider Clock bindings for Marvell MVEBU SoCs
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The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = nand (NAND clock)
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Required properties:
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- compatible : must be "marvell,armada-370-corediv-clock",
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"marvell,armada-375-corediv-clock",
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"marvell,armada-380-corediv-clock",
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"marvell,mv98dx3236-corediv-clock",
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- reg : must be the register address of Core Divider control register
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- #clock-cells : from common clock binding; shall be set to 1
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- clocks : must be set to the parent's phandle
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Example:
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corediv_clk: corediv-clocks@18740 {
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compatible = "marvell,armada-370-corediv-clock";
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reg = <0x18740 0xc>;
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#clock-cells = <1>;
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clocks = <&pll>;
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};
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