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This add the DT bindings documentation for the Sparx5 SoC DPLL clock Link: https://lore.kernel.org/r/20200615133242.24911-7-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
53 lines
1022 B
YAML
53 lines
1022 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Sparx5 DPLL Clock
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maintainers:
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- Lars Povlsen <lars.povlsen@microchip.com>
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description: |
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The Sparx5 DPLL clock controller generates and supplies clock to
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various peripherals within the SoC.
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properties:
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compatible:
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const: microchip,sparx5-dpll
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Clock provider for eMMC:
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- |
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lcpll_clk: lcpll-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <2500000000>;
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};
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clks: clock-controller@61110000c {
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compatible = "microchip,sparx5-dpll";
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#clock-cells = <1>;
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clocks = <&lcpll_clk>;
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reg = <0x1110000c 0x24>;
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};
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...
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