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84e85359f4
The Devicetree bindings document does not have to say in the title that
it is a "binding", but instead just describe the hardware.
Drop trailing "bindings" in various forms (also with trailing full
stop):
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [bB]indings\?\.\?$/title: \1/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com> # ROHM
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # cpufreq
Link: https://lore.kernel.org/r/20221216163815.522628-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
81 lines
2.3 KiB
YAML
81 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire Clock Control Module
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maintainers:
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- Daire McNamara <daire.mcnamara@microchip.com>
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description: |
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Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
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which gates and enables all peripheral clocks.
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This device tree binding describes 33 gate clocks. Clocks are referenced by
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user nodes by the CLKCFG node phandle and the clock index in the group, from
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0 to 32.
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properties:
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compatible:
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const: microchip,mpfs-clkcfg
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reg:
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items:
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- description: |
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clock config registers:
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These registers contain enable, reset & divider tables for the, cpu,
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axi, ahb and rtc/mtimer reference clocks as well as enable and reset
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for the peripheral clocks.
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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resets:
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maxItems: 1
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'#reset-cells':
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description:
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The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
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CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
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peripheral via the clock ID in its "resets" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Clock Config node:
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- |
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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clkcfg: clock-controller@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&ref>;
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#clock-cells = <1>;
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};
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};
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