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0fabe1021f
This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4
[MIPS: DEC: Convert to new irq_chip functions] and
5359b938c0 [MIPS: DECstation I/O ASIC DMA
interrupt handling fix] and implements automatic handling of the two
classes of DMA interrupts the I/O ASIC implements, informational and
errors.
Informational DMA interrupts do not stop the transfer and use the
`handle_edge_irq' handler that clears the request right away so that
another request may be recorded while the previous is being handled.
DMA error interrupts stop the transfer and require a corrective action
before DMA can be reenabled. Therefore they use the `handle_fasteoi_irq'
handler that only clears the request on the way out. Because MIPS
processor interrupt inputs, one of which the I/O ASIC's interrupt
controller is cascaded to, are level-triggered it is recommended that
error DMA interrupt action handlers are registered with the IRQF_ONESHOT
flag set so that they are run with the interrupt line masked.
This change removes the export of clear_ioasic_dma_irq that now does not
have to be called by device drivers to clear interrupts explicitly
anymore. Originally these interrupts were cleared in the .end handler of
the `irq_chip' structure, before it was removed.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5874/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
39 lines
862 B
C
39 lines
862 B
C
/*
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* include/asm-mips/dec/ioasic.h
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*
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* DEC I/O ASIC access operations.
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*
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* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __ASM_DEC_IOASIC_H
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#define __ASM_DEC_IOASIC_H
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#include <linux/spinlock.h>
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#include <linux/types.h>
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extern spinlock_t ioasic_ssr_lock;
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extern volatile u32 *ioasic_base;
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static inline void ioasic_write(unsigned int reg, u32 v)
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{
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ioasic_base[reg / 4] = v;
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}
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static inline u32 ioasic_read(unsigned int reg)
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{
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return ioasic_base[reg / 4];
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}
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extern void init_ioasic_irqs(int base);
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extern int dec_ioasic_clocksource_init(void);
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#endif /* __ASM_DEC_IOASIC_H */
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