mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-18 09:44:18 +08:00
fb1c8f93d8
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
152 lines
3.3 KiB
C
152 lines
3.3 KiB
C
#ifndef __ASM_SPINLOCK_H
|
|
#define __ASM_SPINLOCK_H
|
|
|
|
#include <asm/system.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/spinlock_types.h>
|
|
|
|
/* Note that PA-RISC has to use `1' to mean unlocked and `0' to mean locked
|
|
* since it only has load-and-zero. Moreover, at least on some PA processors,
|
|
* the semaphore address has to be 16-byte aligned.
|
|
*/
|
|
|
|
static inline int __raw_spin_is_locked(raw_spinlock_t *x)
|
|
{
|
|
volatile unsigned int *a = __ldcw_align(x);
|
|
return *a == 0;
|
|
}
|
|
|
|
#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
|
|
#define __raw_spin_unlock_wait(x) \
|
|
do { cpu_relax(); } while (__raw_spin_is_locked(x))
|
|
|
|
static inline void __raw_spin_lock(raw_spinlock_t *x)
|
|
{
|
|
volatile unsigned int *a;
|
|
|
|
mb();
|
|
a = __ldcw_align(x);
|
|
while (__ldcw(a) == 0)
|
|
while (*a == 0);
|
|
mb();
|
|
}
|
|
|
|
static inline void __raw_spin_unlock(raw_spinlock_t *x)
|
|
{
|
|
volatile unsigned int *a;
|
|
mb();
|
|
a = __ldcw_align(x);
|
|
*a = 1;
|
|
mb();
|
|
}
|
|
|
|
static inline int __raw_spin_trylock(raw_spinlock_t *x)
|
|
{
|
|
volatile unsigned int *a;
|
|
int ret;
|
|
|
|
mb();
|
|
a = __ldcw_align(x);
|
|
ret = __ldcw(a) != 0;
|
|
mb();
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Read-write spinlocks, allowing multiple readers
|
|
* but only one writer.
|
|
*/
|
|
|
|
#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
|
|
|
|
/* read_lock, read_unlock are pretty straightforward. Of course it somehow
|
|
* sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */
|
|
|
|
static __inline__ void __raw_read_lock(raw_rwlock_t *rw)
|
|
{
|
|
unsigned long flags;
|
|
local_irq_save(flags);
|
|
__raw_spin_lock(&rw->lock);
|
|
|
|
rw->counter++;
|
|
|
|
__raw_spin_unlock(&rw->lock);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
|
|
{
|
|
unsigned long flags;
|
|
local_irq_save(flags);
|
|
__raw_spin_lock(&rw->lock);
|
|
|
|
rw->counter--;
|
|
|
|
__raw_spin_unlock(&rw->lock);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/* write_lock is less trivial. We optimistically grab the lock and check
|
|
* if we surprised any readers. If so we release the lock and wait till
|
|
* they're all gone before trying again
|
|
*
|
|
* Also note that we don't use the _irqsave / _irqrestore suffixes here.
|
|
* If we're called with interrupts enabled and we've got readers (or other
|
|
* writers) in interrupt handlers someone fucked up and we'd dead-lock
|
|
* sooner or later anyway. prumpf */
|
|
|
|
static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
|
|
{
|
|
retry:
|
|
__raw_spin_lock(&rw->lock);
|
|
|
|
if(rw->counter != 0) {
|
|
/* this basically never happens */
|
|
__raw_spin_unlock(&rw->lock);
|
|
|
|
while (rw->counter != 0)
|
|
cpu_relax();
|
|
|
|
goto retry;
|
|
}
|
|
|
|
/* got it. now leave without unlocking */
|
|
rw->counter = -1; /* remember we are locked */
|
|
}
|
|
|
|
/* write_unlock is absolutely trivial - we don't have to wait for anything */
|
|
|
|
static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
|
|
{
|
|
rw->counter = 0;
|
|
__raw_spin_unlock(&rw->lock);
|
|
}
|
|
|
|
static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
|
|
{
|
|
__raw_spin_lock(&rw->lock);
|
|
if (rw->counter != 0) {
|
|
/* this basically never happens */
|
|
__raw_spin_unlock(&rw->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* got it. now leave without unlocking */
|
|
rw->counter = -1; /* remember we are locked */
|
|
return 1;
|
|
}
|
|
|
|
static __inline__ int __raw_is_read_locked(raw_rwlock_t *rw)
|
|
{
|
|
return rw->counter > 0;
|
|
}
|
|
|
|
static __inline__ int __raw_is_write_locked(raw_rwlock_t *rw)
|
|
{
|
|
return rw->counter < 0;
|
|
}
|
|
|
|
#endif /* __ASM_SPINLOCK_H */
|