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6a27f1a81d
i40iw_hmc.[ch] are to manage hmc for the device. Acked-by: Anjali Singhai Jain <anjali.singhai@intel.com> Acked-by: Shannon Nelson <shannon.nelson@intel.com> Signed-off-by: Faisal Latif <faisal.latif@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
242 lines
7.2 KiB
C
242 lines
7.2 KiB
C
/*******************************************************************************
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*
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* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*******************************************************************************/
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#ifndef I40IW_HMC_H
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#define I40IW_HMC_H
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#include "i40iw_d.h"
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struct i40iw_hw;
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enum i40iw_status_code;
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#define I40IW_HMC_MAX_BP_COUNT 512
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#define I40IW_MAX_SD_ENTRIES 11
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#define I40IW_HW_DBG_HMC_INVALID_BP_MARK 0xCA
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#define I40IW_HMC_INFO_SIGNATURE 0x484D5347
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#define I40IW_HMC_PD_CNT_IN_SD 512
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#define I40IW_HMC_DIRECT_BP_SIZE 0x200000
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#define I40IW_HMC_MAX_SD_COUNT 4096
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#define I40IW_HMC_PAGED_BP_SIZE 4096
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#define I40IW_HMC_PD_BP_BUF_ALIGNMENT 4096
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#define I40IW_FIRST_VF_FPM_ID 16
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#define FPM_MULTIPLIER 1024
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#define I40IW_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++)
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#define I40IW_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++)
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#define I40IW_INC_BP_REFCNT(bp) ((bp)->ref_cnt++)
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#define I40IW_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--)
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#define I40IW_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--)
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#define I40IW_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--)
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/**
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* I40IW_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
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* @hw: pointer to our hw struct
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* @sd_idx: segment descriptor index
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* @pd_idx: page descriptor index
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*/
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#define I40IW_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \
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i40iw_wr32((hw), I40E_PFHMC_PDINV, \
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(((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \
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(0x1 << I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT) | \
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((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
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/**
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* I40IW_INVALIDATE_VF_HMC_PD - Invalidates the pd cache in the hardware
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* @hw: pointer to our hw struct
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* @sd_idx: segment descriptor index
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* @pd_idx: page descriptor index
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* @hmc_fn_id: VF's function id
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*/
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#define I40IW_INVALIDATE_VF_HMC_PD(hw, sd_idx, pd_idx, hmc_fn_id) \
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i40iw_wr32(hw, I40E_GLHMC_VFPDINV(hmc_fn_id - I40IW_FIRST_VF_FPM_ID), \
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((sd_idx << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \
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(pd_idx << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
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struct i40iw_hmc_obj_info {
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u64 base;
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u32 max_cnt;
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u32 cnt;
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u64 size;
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};
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enum i40iw_sd_entry_type {
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I40IW_SD_TYPE_INVALID = 0,
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I40IW_SD_TYPE_PAGED = 1,
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I40IW_SD_TYPE_DIRECT = 2
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};
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struct i40iw_hmc_bp {
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enum i40iw_sd_entry_type entry_type;
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struct i40iw_dma_mem addr;
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u32 sd_pd_index;
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u32 ref_cnt;
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};
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struct i40iw_hmc_pd_entry {
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struct i40iw_hmc_bp bp;
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u32 sd_index;
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bool rsrc_pg;
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bool valid;
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};
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struct i40iw_hmc_pd_table {
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struct i40iw_dma_mem pd_page_addr;
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struct i40iw_hmc_pd_entry *pd_entry;
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struct i40iw_virt_mem pd_entry_virt_mem;
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u32 ref_cnt;
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u32 sd_index;
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};
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struct i40iw_hmc_sd_entry {
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enum i40iw_sd_entry_type entry_type;
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bool valid;
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union {
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struct i40iw_hmc_pd_table pd_table;
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struct i40iw_hmc_bp bp;
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} u;
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};
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struct i40iw_hmc_sd_table {
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struct i40iw_virt_mem addr;
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u32 sd_cnt;
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u32 ref_cnt;
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struct i40iw_hmc_sd_entry *sd_entry;
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};
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struct i40iw_hmc_info {
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u32 signature;
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u8 hmc_fn_id;
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u16 first_sd_index;
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struct i40iw_hmc_obj_info *hmc_obj;
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struct i40iw_virt_mem hmc_obj_virt_mem;
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struct i40iw_hmc_sd_table sd_table;
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u16 sd_indexes[I40IW_HMC_MAX_SD_COUNT];
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};
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struct update_sd_entry {
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u64 cmd;
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u64 data;
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};
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struct i40iw_update_sds_info {
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u32 cnt;
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u8 hmc_fn_id;
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struct update_sd_entry entry[I40IW_MAX_SD_ENTRIES];
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};
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struct i40iw_ccq_cqe_info;
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struct i40iw_hmc_fcn_info {
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void (*callback_fcn)(struct i40iw_sc_dev *, void *,
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struct i40iw_ccq_cqe_info *);
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void *cqp_callback_param;
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u32 vf_id;
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u16 iw_vf_idx;
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bool free_fcn;
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};
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enum i40iw_hmc_rsrc_type {
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I40IW_HMC_IW_QP = 0,
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I40IW_HMC_IW_CQ = 1,
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I40IW_HMC_IW_SRQ = 2,
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I40IW_HMC_IW_HTE = 3,
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I40IW_HMC_IW_ARP = 4,
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I40IW_HMC_IW_APBVT_ENTRY = 5,
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I40IW_HMC_IW_MR = 6,
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I40IW_HMC_IW_XF = 7,
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I40IW_HMC_IW_XFFL = 8,
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I40IW_HMC_IW_Q1 = 9,
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I40IW_HMC_IW_Q1FL = 10,
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I40IW_HMC_IW_TIMER = 11,
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I40IW_HMC_IW_FSIMC = 12,
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I40IW_HMC_IW_FSIAV = 13,
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I40IW_HMC_IW_PBLE = 14,
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I40IW_HMC_IW_MAX = 15,
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};
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struct i40iw_hmc_create_obj_info {
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struct i40iw_hmc_info *hmc_info;
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struct i40iw_virt_mem add_sd_virt_mem;
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u32 rsrc_type;
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u32 start_idx;
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u32 count;
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u32 add_sd_cnt;
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enum i40iw_sd_entry_type entry_type;
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bool is_pf;
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};
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struct i40iw_hmc_del_obj_info {
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struct i40iw_hmc_info *hmc_info;
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struct i40iw_virt_mem del_sd_virt_mem;
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u32 rsrc_type;
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u32 start_idx;
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u32 count;
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u32 del_sd_cnt;
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bool is_pf;
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};
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enum i40iw_status_code i40iw_copy_dma_mem(struct i40iw_hw *hw, void *dest_buf,
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struct i40iw_dma_mem *src_mem, u64 src_offset, u64 size);
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enum i40iw_status_code i40iw_sc_create_hmc_obj(struct i40iw_sc_dev *dev,
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struct i40iw_hmc_create_obj_info *info);
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enum i40iw_status_code i40iw_sc_del_hmc_obj(struct i40iw_sc_dev *dev,
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struct i40iw_hmc_del_obj_info *info,
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bool reset);
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enum i40iw_status_code i40iw_hmc_sd_one(struct i40iw_sc_dev *dev, u8 hmc_fn_id,
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u64 pa, u32 sd_idx, enum i40iw_sd_entry_type type,
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bool setsd);
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enum i40iw_status_code i40iw_update_sds_noccq(struct i40iw_sc_dev *dev,
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struct i40iw_update_sds_info *info);
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struct i40iw_vfdev *i40iw_vfdev_from_fpm(struct i40iw_sc_dev *dev, u8 hmc_fn_id);
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struct i40iw_hmc_info *i40iw_vf_hmcinfo_from_fpm(struct i40iw_sc_dev *dev,
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u8 hmc_fn_id);
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enum i40iw_status_code i40iw_add_sd_table_entry(struct i40iw_hw *hw,
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struct i40iw_hmc_info *hmc_info, u32 sd_index,
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enum i40iw_sd_entry_type type, u64 direct_mode_sz);
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enum i40iw_status_code i40iw_add_pd_table_entry(struct i40iw_hw *hw,
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struct i40iw_hmc_info *hmc_info, u32 pd_index,
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struct i40iw_dma_mem *rsrc_pg);
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enum i40iw_status_code i40iw_remove_pd_bp(struct i40iw_hw *hw,
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struct i40iw_hmc_info *hmc_info, u32 idx, bool is_pf);
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enum i40iw_status_code i40iw_prep_remove_sd_bp(struct i40iw_hmc_info *hmc_info, u32 idx);
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enum i40iw_status_code i40iw_prep_remove_pd_page(struct i40iw_hmc_info *hmc_info, u32 idx);
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#define ENTER_SHARED_FUNCTION()
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#define EXIT_SHARED_FUNCTION()
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#endif /* I40IW_HMC_H */
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