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8c452a8898
Since commit 0f0581b24b ("spi: fsl: Convert to use CS GPIO
descriptors"), the prefered way to define chipselect GPIOs is using
'cs-gpios' property instead of the legacy 'gpios' property.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/7556683b57d8ce100855857f03d1cd3d2903d045.1574943062.git.christophe.leroy@c-s.fr
364 lines
8.5 KiB
Plaintext
364 lines
8.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC832x RDB Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*/
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/dts-v1/;
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/ {
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model = "MPC8323ERDB";
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compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet1;
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ethernet1 = &enet0;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8323@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <16384>; // L1, 16K
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i-cache-size = <16384>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x04000000>;
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};
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soc8323@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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pmc: power@b00 {
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compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 0x8>;
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interrupt-parent = <&ipic>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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cell-index = <3>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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crypto@30000 {
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compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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fsl,num-channels = <1>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x4c>;
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fsl,descriptor-types-mask = <0x0122003f>;
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sleep = <&pmc 0x03000000>;
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};
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ipic:pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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par_io@1400 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1400 0x100>;
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ranges = <3 0x1448 0x18>;
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compatible = "fsl,mpc8323-qe-pario";
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device_type = "par_io";
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num-ports = <7>;
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qe_pio_d: gpio-controller@1448 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8323-qe-pario-bank";
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reg = <3 0x18>;
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gpio-controller;
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};
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ucc2pio:ucc_pin@2 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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3 4 3 0 2 0 /* MDIO */
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3 5 1 0 2 0 /* MDC */
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3 21 2 0 1 0 /* RX_CLK (CLK16) */
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3 23 2 0 1 0 /* TX_CLK (CLK3) */
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0 18 1 0 1 0 /* TxD0 */
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0 19 1 0 1 0 /* TxD1 */
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0 20 1 0 1 0 /* TxD2 */
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0 21 1 0 1 0 /* TxD3 */
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0 22 2 0 1 0 /* RxD0 */
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0 23 2 0 1 0 /* RxD1 */
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0 24 2 0 1 0 /* RxD2 */
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0 25 2 0 1 0 /* RxD3 */
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0 26 2 0 1 0 /* RX_ER */
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0 27 1 0 1 0 /* TX_ER */
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0 28 2 0 1 0 /* RX_DV */
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0 29 2 0 1 0 /* COL */
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0 30 1 0 1 0 /* TX_EN */
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0 31 2 0 1 0>; /* CRS */
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};
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ucc3pio:ucc_pin@3 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 13 2 0 1 0 /* RX_CLK (CLK9) */
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3 24 2 0 1 0 /* TX_CLK (CLK10) */
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1 0 1 0 1 0 /* TxD0 */
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1 1 1 0 1 0 /* TxD1 */
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1 2 1 0 1 0 /* TxD2 */
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1 3 1 0 1 0 /* TxD3 */
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1 4 2 0 1 0 /* RxD0 */
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1 5 2 0 1 0 /* RxD1 */
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1 6 2 0 1 0 /* RxD2 */
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1 7 2 0 1 0 /* RxD3 */
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1 8 2 0 1 0 /* RX_ER */
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1 9 1 0 1 0 /* TX_ER */
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1 10 2 0 1 0 /* RX_DV */
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1 11 2 0 1 0 /* COL */
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1 12 1 0 1 0 /* TX_EN */
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1 13 2 0 1 0>; /* CRS */
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};
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};
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};
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qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xe0100000 0x00100000>;
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reg = <0xe0100000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <198000000>;
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fsl,qe-num-riscs = <1>;
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fsl,qe-num-snums = <28>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x00010000 0x00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x4000>;
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};
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};
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spi@4c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x4c0 0x40>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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cs-gpios = <&qe_pio_d 13 0>;
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mode = "cpu-qe";
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mmc-slot@0 {
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compatible = "fsl,mpc8323rdb-mmc-slot",
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"mmc-spi-slot";
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reg = <0>;
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gpios = <&qe_pio_d 14 1
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&qe_pio_d 15 0>;
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voltage-ranges = <3300 3300>;
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spi-max-frequency = <50000000>;
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};
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};
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spi@500 {
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cell-index = <1>;
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compatible = "fsl,spi";
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reg = <0x500 0x40>;
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interrupts = <1>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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enet0: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <2>;
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reg = <0x3000 0x200>;
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interrupts = <33>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk16";
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tx-clock-name = "clk3";
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phy-handle = <&phy00>;
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pio-handle = <&ucc2pio>;
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};
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enet1: ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <3>;
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reg = <0x2200 0x200>;
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interrupts = <34>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk9";
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tx-clock-name = "clk10";
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phy-handle = <&phy04>;
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pio-handle = <&ucc3pio>;
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};
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mdio@3120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3120 0x18>;
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compatible = "fsl,ucc-mdio";
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phy00:ethernet-phy@0 {
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reg = <0x0>;
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};
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phy04:ethernet-phy@4 {
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reg = <0x4>;
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};
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};
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qeic:interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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big-endian;
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interrupts = <32 0x8 33 0x8>; //high:32 low:33
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interrupt-parent = <&ipic>;
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};
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};
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pci0: pci@e0008500 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x10 AD16 (USB) */
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0x8000 0x0 0x0 0x1 &ipic 17 0x8
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/* IDSEL 0x11 AD17 (Mini1)*/
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0x8800 0x0 0x0 0x1 &ipic 18 0x8
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0x8800 0x0 0x0 0x2 &ipic 19 0x8
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0x8800 0x0 0x0 0x3 &ipic 20 0x8
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0x8800 0x0 0x0 0x4 &ipic 48 0x8
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/* IDSEL 0x12 AD18 (PCI/Mini2) */
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0x9000 0x0 0x0 0x1 &ipic 19 0x8
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0x9000 0x0 0x0 0x2 &ipic 20 0x8
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0x9000 0x0 0x0 0x3 &ipic 48 0x8
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0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100 /* internal registers */
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0xe0008300 0x8>; /* config space access registers */
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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sleep = <&pmc 0x00010000>;
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};
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};
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