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c6ff132d42
A lot of header files are only used internally now, so they can be moved to mach-s3c, out of the visibility of drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200806182059.2431-40-krzk@kernel.org [krzk: Rebase and fixup leds-s3c24xx driver] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2004 Shannon Holland <holland@loser.net>
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*
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* S3C2410 ADC registers
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*/
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#ifndef __ASM_ARCH_REGS_ADC_H
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#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
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#define S3C2410_ADCREG(x) (x)
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#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
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#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
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#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
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#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
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#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
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#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
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#define S3C2443_ADCMUX S3C2410_ADCREG(0x18)
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#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
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#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
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#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
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/* ADCCON Register Bits */
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#define S3C64XX_ADCCON_RESSEL (1<<16)
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#define S3C2410_ADCCON_ECFLG (1<<15)
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#define S3C2410_ADCCON_PRSCEN (1<<14)
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#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
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#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
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#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
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#define S3C2410_ADCCON_MUXMASK (0x7<<3)
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#define S3C2416_ADCCON_RESSEL (1 << 3)
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#define S3C2410_ADCCON_STDBM (1<<2)
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#define S3C2410_ADCCON_READ_START (1<<1)
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#define S3C2410_ADCCON_ENABLE_START (1<<0)
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#define S3C2410_ADCCON_STARTMASK (0x3<<0)
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/* ADCTSC Register Bits */
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#define S3C2443_ADCTSC_UD_SEN (1 << 8)
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#define S3C2410_ADCTSC_YM_SEN (1<<7)
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#define S3C2410_ADCTSC_YP_SEN (1<<6)
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#define S3C2410_ADCTSC_XM_SEN (1<<5)
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#define S3C2410_ADCTSC_XP_SEN (1<<4)
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#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
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#define S3C2410_ADCTSC_AUTO_PST (1<<2)
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#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
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/* ADCDAT0 Bits */
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#define S3C2410_ADCDAT0_UPDOWN (1<<15)
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#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
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#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
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#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
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/* ADCDAT1 Bits */
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#define S3C2410_ADCDAT1_UPDOWN (1<<15)
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#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
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#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
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#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
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#endif /* __ASM_ARCH_REGS_ADC_H */
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