Zong Li 263ac39085 clk: sifive: Fix the wrong bit field shift ... The clk enable bit should be 31 instead of 24. Signed-off-by: Zong Li <zong.li@sifive.com> Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com> Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2020-12-16 12:23:12 -08:00
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fu540-prci.c	clk: sifive: Extract prci core to common base	2020-12-16 12:22:39 -08:00
fu540-prci.h	clk: sifive: Extract prci core to common base	2020-12-16 12:22:39 -08:00
fu740-prci.c	clk: sifive: Add a driver for the SiFive FU740 PRCI IP block	2020-12-16 12:22:59 -08:00
fu740-prci.h	clk: sifive: Add a driver for the SiFive FU740 PRCI IP block	2020-12-16 12:22:59 -08:00
Kconfig	clk: sifive: Add a driver for the SiFive FU740 PRCI IP block	2020-12-16 12:22:59 -08:00
Makefile	clk: sifive: Add a driver for the SiFive FU740 PRCI IP block	2020-12-16 12:22:59 -08:00
sifive-prci.c	clk: sifive: Add a driver for the SiFive FU740 PRCI IP block	2020-12-16 12:22:59 -08:00
sifive-prci.h	clk: sifive: Fix the wrong bit field shift	2020-12-16 12:23:12 -08:00