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In preparation for adding CQHCI crypto engine (inline encryption) support, add the code required to make mmc_core and mmc_block aware of inline encryption. Specifically: - Add a capability flag MMC_CAP2_CRYPTO to struct mmc_host. Drivers will set this if the host and driver support inline encryption. - Embed a blk_keyslot_manager in struct mmc_host. Drivers will initialize this (as a device-managed resource) if the host and driver support inline encryption. mmc_block registers this keyslot manager with the request_queue of any MMC card attached to the host. - Make mmc_block copy the crypto keyslot and crypto data unit number from struct request to struct mmc_request, so that drivers will have access to them. - If the MMC host is reset, reprogram all the keyslots to ensure that the software state stays in sync with the hardware state. Co-developed-by: Satya Tangirala <satyat@google.com> Signed-off-by: Satya Tangirala <satyat@google.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Satya Tangirala <satyat@google.com> Reviewed-and-tested-by: Peng Zhou <peng.zhou@mediatek.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210126001456.382989-2-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
22 lines
705 B
Makefile
22 lines
705 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the kernel mmc core.
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#
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obj-$(CONFIG_MMC) += mmc_core.o
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mmc_core-y := core.o bus.o host.o \
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mmc.o mmc_ops.o sd.o sd_ops.o \
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sdio.o sdio_ops.o sdio_bus.o \
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sdio_cis.o sdio_io.o sdio_irq.o \
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slot-gpio.o regulator.o
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mmc_core-$(CONFIG_OF) += pwrseq.o
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obj-$(CONFIG_PWRSEQ_SIMPLE) += pwrseq_simple.o
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obj-$(CONFIG_PWRSEQ_SD8787) += pwrseq_sd8787.o
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obj-$(CONFIG_PWRSEQ_EMMC) += pwrseq_emmc.o
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mmc_core-$(CONFIG_DEBUG_FS) += debugfs.o
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obj-$(CONFIG_MMC_BLOCK) += mmc_block.o
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mmc_block-objs := block.o queue.o
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obj-$(CONFIG_MMC_TEST) += mmc_test.o
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obj-$(CONFIG_SDIO_UART) += sdio_uart.o
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mmc_core-$(CONFIG_MMC_CRYPTO) += crypto.o
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