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396e13e115
In current driver, buffer2 available only when hardware supports split
header. Wrongly set buffer2 valid in stmmac_rx_refill when refill buffer
address. You can see that desc3 is 0x81000000 after initialization, but
turn out to be 0x83000000 after refill.
Fixes: 67afd6d1cf ("net: stmmac: Add Split Header support and enable it in XGMAC cores")
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
380 lines
8.9 KiB
C
380 lines
8.9 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
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* stmmac XGMAC support.
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*/
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#include <linux/stmmac.h>
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#include "common.h"
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#include "dwxgmac2.h"
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static int dwxgmac2_get_tx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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int ret = tx_done;
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if (unlikely(tdes3 & XGMAC_TDES3_OWN))
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return tx_dma_own;
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if (likely(!(tdes3 & XGMAC_TDES3_LD)))
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return tx_not_ls;
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return ret;
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}
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static int dwxgmac2_get_rx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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unsigned int rdes3 = le32_to_cpu(p->des3);
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if (unlikely(rdes3 & XGMAC_RDES3_OWN))
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return dma_own;
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if (unlikely(rdes3 & XGMAC_RDES3_CTXT))
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return discard_frame;
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if (likely(!(rdes3 & XGMAC_RDES3_LD)))
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return rx_not_ls;
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if (unlikely((rdes3 & XGMAC_RDES3_ES) && (rdes3 & XGMAC_RDES3_LD)))
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return discard_frame;
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return good_frame;
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}
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static int dwxgmac2_get_tx_len(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
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}
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static int dwxgmac2_get_tx_owner(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0;
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}
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static void dwxgmac2_set_tx_owner(struct dma_desc *p)
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{
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p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN);
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}
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static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
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{
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p->des3 |= cpu_to_le32(XGMAC_RDES3_OWN);
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if (!disable_rx_ic)
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p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC);
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}
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static int dwxgmac2_get_tx_ls(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0;
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}
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static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe)
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{
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return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL);
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}
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static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p)
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{
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p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE);
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}
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static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p)
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{
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return 0; /* Not supported */
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}
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static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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u64 ns = 0;
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ns += le32_to_cpu(p->des1) * 1000000000ULL;
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ns += le32_to_cpu(p->des0);
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*ts = ns;
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}
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static int dwxgmac2_rx_check_timestamp(void *desc)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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unsigned int rdes3 = le32_to_cpu(p->des3);
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bool desc_valid, ts_valid;
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dma_rmb();
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desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT);
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ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA);
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if (likely(desc_valid && ts_valid)) {
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if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
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return -EINVAL;
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return 0;
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}
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return -EINVAL;
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}
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static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
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u32 ats)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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unsigned int rdes3 = le32_to_cpu(p->des3);
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int ret = -EBUSY;
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if (likely(rdes3 & XGMAC_RDES3_CDA))
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ret = dwxgmac2_rx_check_timestamp(next_desc);
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return !ret;
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}
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static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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int mode, int end, int bfsize)
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{
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dwxgmac2_set_rx_owner(p, disable_rx_ic);
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}
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static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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bool csum_flag, int mode, bool tx_own,
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bool ls, unsigned int tot_pkt_len)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L);
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tdes3 |= tot_pkt_len & XGMAC_TDES3_FL;
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if (is_fs)
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tdes3 |= XGMAC_TDES3_FD;
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else
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tdes3 &= ~XGMAC_TDES3_FD;
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if (csum_flag)
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tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT;
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else
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tdes3 &= ~XGMAC_TDES3_CIC;
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if (ls)
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tdes3 |= XGMAC_TDES3_LD;
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else
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tdes3 &= ~XGMAC_TDES3_LD;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= XGMAC_TDES3_OWN;
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if (is_fs && tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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dma_wmb();
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p->des3 = cpu_to_le32(tdes3);
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}
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static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
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int len1, int len2, bool tx_own,
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bool ls, unsigned int tcphdrlen,
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unsigned int tcppayloadlen)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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if (len1)
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p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L);
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if (len2)
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p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) &
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XGMAC_TDES2_B2L);
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if (is_fs) {
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tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE;
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tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) &
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XGMAC_TDES3_THL;
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tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL;
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} else {
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tdes3 &= ~XGMAC_TDES3_FD;
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}
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if (ls)
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tdes3 |= XGMAC_TDES3_LD;
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else
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tdes3 &= ~XGMAC_TDES3_LD;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= XGMAC_TDES3_OWN;
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if (is_fs && tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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dma_wmb();
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p->des3 = cpu_to_le32(tdes3);
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}
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static void dwxgmac2_release_tx_desc(struct dma_desc *p, int mode)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static void dwxgmac2_set_tx_ic(struct dma_desc *p)
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{
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p->des2 |= cpu_to_le32(XGMAC_TDES2_IOC);
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}
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static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = cpu_to_le32(mss);
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p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
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}
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static void dwxgmac2_get_addr(struct dma_desc *p, unsigned int *addr)
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{
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*addr = le32_to_cpu(p->des0);
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}
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static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
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{
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p->des0 = cpu_to_le32(lower_32_bits(addr));
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p->des1 = cpu_to_le32(upper_32_bits(addr));
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}
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static void dwxgmac2_clear(struct dma_desc *p)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,
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enum pkt_hash_types *type)
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{
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unsigned int rdes3 = le32_to_cpu(p->des3);
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u32 ptype;
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if (rdes3 & XGMAC_RDES3_RSV) {
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ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT;
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switch (ptype) {
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case XGMAC_L34T_IP4TCP:
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case XGMAC_L34T_IP4UDP:
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case XGMAC_L34T_IP6TCP:
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case XGMAC_L34T_IP6UDP:
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*type = PKT_HASH_TYPE_L4;
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break;
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default:
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*type = PKT_HASH_TYPE_L3;
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break;
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}
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*hash = le32_to_cpu(p->des1);
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return 0;
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}
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return -EINVAL;
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}
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static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)
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{
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if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T)
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*len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
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}
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static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)
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{
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p->des2 = cpu_to_le32(lower_32_bits(addr));
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p->des3 = cpu_to_le32(upper_32_bits(addr));
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}
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static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)
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{
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sarc_type <<= XGMAC_TDES3_SAIC_SHIFT;
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p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC);
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}
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static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
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u32 inner_type)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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/* Inner VLAN */
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if (inner_type) {
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u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT;
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des &= XGMAC_TDES2_IVT;
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p->des2 = cpu_to_le32(des);
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des = inner_type << XGMAC_TDES3_IVTIR_SHIFT;
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des &= XGMAC_TDES3_IVTIR;
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p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV);
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}
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/* Outer VLAN */
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p->des3 |= cpu_to_le32(tag & XGMAC_TDES3_VT);
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p->des3 |= cpu_to_le32(XGMAC_TDES3_VLTV);
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p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT);
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}
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static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)
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{
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type <<= XGMAC_TDES2_VTIR_SHIFT;
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p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
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}
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static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
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{
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p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV);
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p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT);
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p->des6 = 0;
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p->des7 = 0;
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}
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const struct stmmac_desc_ops dwxgmac210_desc_ops = {
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.tx_status = dwxgmac2_get_tx_status,
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.rx_status = dwxgmac2_get_rx_status,
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.get_tx_len = dwxgmac2_get_tx_len,
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.get_tx_owner = dwxgmac2_get_tx_owner,
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.set_tx_owner = dwxgmac2_set_tx_owner,
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.set_rx_owner = dwxgmac2_set_rx_owner,
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.get_tx_ls = dwxgmac2_get_tx_ls,
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.get_rx_frame_len = dwxgmac2_get_rx_frame_len,
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.enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,
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.get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,
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.get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,
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.get_timestamp = dwxgmac2_get_timestamp,
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.set_tx_ic = dwxgmac2_set_tx_ic,
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.prepare_tx_desc = dwxgmac2_prepare_tx_desc,
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.prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,
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.release_tx_desc = dwxgmac2_release_tx_desc,
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.init_rx_desc = dwxgmac2_init_rx_desc,
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.init_tx_desc = dwxgmac2_init_tx_desc,
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.set_mss = dwxgmac2_set_mss,
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.get_addr = dwxgmac2_get_addr,
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.set_addr = dwxgmac2_set_addr,
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.clear = dwxgmac2_clear,
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.get_rx_hash = dwxgmac2_get_rx_hash,
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.get_rx_header_len = dwxgmac2_get_rx_header_len,
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.set_sec_addr = dwxgmac2_set_sec_addr,
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.set_sarc = dwxgmac2_set_sarc,
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.set_vlan_tag = dwxgmac2_set_vlan_tag,
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.set_vlan = dwxgmac2_set_vlan,
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.set_tbs = dwxgmac2_set_tbs,
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};
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