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76d579f251
Set cra_blocksize to 1 to indicate OFB is a stream cipher. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
1301 lines
31 KiB
C
1301 lines
31 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Cryptographic API.
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*
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* Support for ATMEL DES/TDES HW acceleration.
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*
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* Copyright (c) 2012 Eukréa Electromatique - ATMEL
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* Author: Nicolas Royer <nicolas@eukrea.com>
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*
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* Some ideas are from omap-aes.c drivers.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/hw_random.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/of_device.h>
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#include <linux/delay.h>
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#include <linux/crypto.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/algapi.h>
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#include <crypto/internal/des.h>
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#include <crypto/internal/skcipher.h>
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#include "atmel-tdes-regs.h"
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#define ATMEL_TDES_PRIORITY 300
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/* TDES flags */
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/* Reserve bits [17:16], [13:12], [2:0] for AES Mode Register */
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#define TDES_FLAGS_ENCRYPT TDES_MR_CYPHER_ENC
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#define TDES_FLAGS_OPMODE_MASK (TDES_MR_OPMOD_MASK | TDES_MR_CFBS_MASK)
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#define TDES_FLAGS_ECB TDES_MR_OPMOD_ECB
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#define TDES_FLAGS_CBC TDES_MR_OPMOD_CBC
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#define TDES_FLAGS_OFB TDES_MR_OPMOD_OFB
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#define TDES_FLAGS_CFB64 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_64b)
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#define TDES_FLAGS_CFB32 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_32b)
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#define TDES_FLAGS_CFB16 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_16b)
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#define TDES_FLAGS_CFB8 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_8b)
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#define TDES_FLAGS_MODE_MASK (TDES_FLAGS_OPMODE_MASK | TDES_FLAGS_ENCRYPT)
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#define TDES_FLAGS_INIT BIT(3)
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#define TDES_FLAGS_FAST BIT(4)
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#define TDES_FLAGS_BUSY BIT(5)
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#define TDES_FLAGS_DMA BIT(6)
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#define ATMEL_TDES_QUEUE_LENGTH 50
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#define CFB8_BLOCK_SIZE 1
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#define CFB16_BLOCK_SIZE 2
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#define CFB32_BLOCK_SIZE 4
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struct atmel_tdes_caps {
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bool has_dma;
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u32 has_cfb_3keys;
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};
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struct atmel_tdes_dev;
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struct atmel_tdes_ctx {
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struct atmel_tdes_dev *dd;
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int keylen;
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u32 key[DES3_EDE_KEY_SIZE / sizeof(u32)];
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unsigned long flags;
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u16 block_size;
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};
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struct atmel_tdes_reqctx {
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unsigned long mode;
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u8 lastc[DES_BLOCK_SIZE];
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};
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struct atmel_tdes_dma {
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struct dma_chan *chan;
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struct dma_slave_config dma_conf;
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};
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struct atmel_tdes_dev {
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struct list_head list;
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unsigned long phys_base;
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void __iomem *io_base;
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struct atmel_tdes_ctx *ctx;
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struct device *dev;
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struct clk *iclk;
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int irq;
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unsigned long flags;
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spinlock_t lock;
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struct crypto_queue queue;
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struct tasklet_struct done_task;
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struct tasklet_struct queue_task;
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struct skcipher_request *req;
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size_t total;
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struct scatterlist *in_sg;
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unsigned int nb_in_sg;
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size_t in_offset;
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struct scatterlist *out_sg;
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unsigned int nb_out_sg;
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size_t out_offset;
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size_t buflen;
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size_t dma_size;
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void *buf_in;
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int dma_in;
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dma_addr_t dma_addr_in;
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struct atmel_tdes_dma dma_lch_in;
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void *buf_out;
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int dma_out;
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dma_addr_t dma_addr_out;
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struct atmel_tdes_dma dma_lch_out;
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struct atmel_tdes_caps caps;
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u32 hw_version;
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};
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struct atmel_tdes_drv {
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struct list_head dev_list;
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spinlock_t lock;
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};
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static struct atmel_tdes_drv atmel_tdes = {
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.dev_list = LIST_HEAD_INIT(atmel_tdes.dev_list),
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.lock = __SPIN_LOCK_UNLOCKED(atmel_tdes.lock),
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};
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static int atmel_tdes_sg_copy(struct scatterlist **sg, size_t *offset,
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void *buf, size_t buflen, size_t total, int out)
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{
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size_t count, off = 0;
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while (buflen && total) {
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count = min((*sg)->length - *offset, total);
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count = min(count, buflen);
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if (!count)
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return off;
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scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out);
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off += count;
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buflen -= count;
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*offset += count;
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total -= count;
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if (*offset == (*sg)->length) {
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*sg = sg_next(*sg);
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if (*sg)
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*offset = 0;
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else
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total = 0;
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}
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}
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return off;
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}
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static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset)
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{
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return readl_relaxed(dd->io_base + offset);
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}
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static inline void atmel_tdes_write(struct atmel_tdes_dev *dd,
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u32 offset, u32 value)
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{
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writel_relaxed(value, dd->io_base + offset);
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}
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static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset,
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const u32 *value, int count)
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{
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for (; count--; value++, offset += 4)
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atmel_tdes_write(dd, offset, *value);
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}
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static struct atmel_tdes_dev *atmel_tdes_dev_alloc(void)
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{
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struct atmel_tdes_dev *tdes_dd;
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spin_lock_bh(&atmel_tdes.lock);
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/* One TDES IP per SoC. */
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tdes_dd = list_first_entry_or_null(&atmel_tdes.dev_list,
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struct atmel_tdes_dev, list);
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spin_unlock_bh(&atmel_tdes.lock);
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return tdes_dd;
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}
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static int atmel_tdes_hw_init(struct atmel_tdes_dev *dd)
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{
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int err;
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err = clk_prepare_enable(dd->iclk);
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if (err)
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return err;
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if (!(dd->flags & TDES_FLAGS_INIT)) {
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atmel_tdes_write(dd, TDES_CR, TDES_CR_SWRST);
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dd->flags |= TDES_FLAGS_INIT;
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}
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return 0;
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}
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static inline unsigned int atmel_tdes_get_version(struct atmel_tdes_dev *dd)
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{
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return atmel_tdes_read(dd, TDES_HW_VERSION) & 0x00000fff;
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}
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static int atmel_tdes_hw_version_init(struct atmel_tdes_dev *dd)
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{
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int err;
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err = atmel_tdes_hw_init(dd);
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if (err)
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return err;
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dd->hw_version = atmel_tdes_get_version(dd);
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dev_info(dd->dev,
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"version: 0x%x\n", dd->hw_version);
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clk_disable_unprepare(dd->iclk);
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return 0;
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}
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static void atmel_tdes_dma_callback(void *data)
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{
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struct atmel_tdes_dev *dd = data;
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/* dma_lch_out - completed */
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tasklet_schedule(&dd->done_task);
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}
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static int atmel_tdes_write_ctrl(struct atmel_tdes_dev *dd)
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{
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int err;
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u32 valmr = TDES_MR_SMOD_PDC;
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err = atmel_tdes_hw_init(dd);
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if (err)
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return err;
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if (!dd->caps.has_dma)
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atmel_tdes_write(dd, TDES_PTCR,
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TDES_PTCR_TXTDIS | TDES_PTCR_RXTDIS);
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/* MR register must be set before IV registers */
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if (dd->ctx->keylen > (DES_KEY_SIZE << 1)) {
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valmr |= TDES_MR_KEYMOD_3KEY;
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valmr |= TDES_MR_TDESMOD_TDES;
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} else if (dd->ctx->keylen > DES_KEY_SIZE) {
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valmr |= TDES_MR_KEYMOD_2KEY;
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valmr |= TDES_MR_TDESMOD_TDES;
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} else {
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valmr |= TDES_MR_TDESMOD_DES;
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}
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valmr |= dd->flags & TDES_FLAGS_MODE_MASK;
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atmel_tdes_write(dd, TDES_MR, valmr);
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atmel_tdes_write_n(dd, TDES_KEY1W1R, dd->ctx->key,
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dd->ctx->keylen >> 2);
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if (dd->req->iv && (valmr & TDES_MR_OPMOD_MASK) != TDES_MR_OPMOD_ECB)
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atmel_tdes_write_n(dd, TDES_IV1R, (void *)dd->req->iv, 2);
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return 0;
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}
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static int atmel_tdes_crypt_pdc_stop(struct atmel_tdes_dev *dd)
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{
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int err = 0;
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size_t count;
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atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
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if (dd->flags & TDES_FLAGS_FAST) {
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dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
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dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
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} else {
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dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
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dd->dma_size, DMA_FROM_DEVICE);
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/* copy data */
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count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
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dd->buf_out, dd->buflen, dd->dma_size, 1);
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if (count != dd->dma_size) {
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err = -EINVAL;
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dev_dbg(dd->dev, "not all data converted: %zu\n", count);
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}
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}
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return err;
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}
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static int atmel_tdes_buff_init(struct atmel_tdes_dev *dd)
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{
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int err = -ENOMEM;
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dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0);
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dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0);
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dd->buflen = PAGE_SIZE;
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dd->buflen &= ~(DES_BLOCK_SIZE - 1);
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if (!dd->buf_in || !dd->buf_out) {
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dev_dbg(dd->dev, "unable to alloc pages.\n");
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goto err_alloc;
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}
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/* MAP here */
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dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in,
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dd->buflen, DMA_TO_DEVICE);
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err = dma_mapping_error(dd->dev, dd->dma_addr_in);
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if (err) {
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dev_dbg(dd->dev, "dma %zd bytes error\n", dd->buflen);
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goto err_map_in;
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}
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dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out,
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dd->buflen, DMA_FROM_DEVICE);
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err = dma_mapping_error(dd->dev, dd->dma_addr_out);
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if (err) {
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dev_dbg(dd->dev, "dma %zd bytes error\n", dd->buflen);
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goto err_map_out;
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}
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return 0;
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err_map_out:
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dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
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DMA_TO_DEVICE);
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err_map_in:
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err_alloc:
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free_page((unsigned long)dd->buf_out);
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free_page((unsigned long)dd->buf_in);
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return err;
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}
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static void atmel_tdes_buff_cleanup(struct atmel_tdes_dev *dd)
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{
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dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
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DMA_FROM_DEVICE);
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dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
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DMA_TO_DEVICE);
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free_page((unsigned long)dd->buf_out);
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free_page((unsigned long)dd->buf_in);
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}
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static int atmel_tdes_crypt_pdc(struct atmel_tdes_dev *dd,
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dma_addr_t dma_addr_in,
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dma_addr_t dma_addr_out, int length)
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{
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struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd->req);
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int len32;
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dd->dma_size = length;
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if (!(dd->flags & TDES_FLAGS_FAST)) {
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dma_sync_single_for_device(dd->dev, dma_addr_in, length,
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DMA_TO_DEVICE);
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}
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switch (rctx->mode & TDES_FLAGS_OPMODE_MASK) {
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case TDES_FLAGS_CFB8:
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len32 = DIV_ROUND_UP(length, sizeof(u8));
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break;
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case TDES_FLAGS_CFB16:
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len32 = DIV_ROUND_UP(length, sizeof(u16));
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break;
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default:
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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break;
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}
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atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
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atmel_tdes_write(dd, TDES_TPR, dma_addr_in);
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atmel_tdes_write(dd, TDES_TCR, len32);
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atmel_tdes_write(dd, TDES_RPR, dma_addr_out);
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atmel_tdes_write(dd, TDES_RCR, len32);
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/* Enable Interrupt */
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atmel_tdes_write(dd, TDES_IER, TDES_INT_ENDRX);
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/* Start DMA transfer */
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atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTEN | TDES_PTCR_RXTEN);
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return 0;
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}
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static int atmel_tdes_crypt_dma(struct atmel_tdes_dev *dd,
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dma_addr_t dma_addr_in,
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dma_addr_t dma_addr_out, int length)
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{
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struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd->req);
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struct scatterlist sg[2];
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struct dma_async_tx_descriptor *in_desc, *out_desc;
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enum dma_slave_buswidth addr_width;
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dd->dma_size = length;
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if (!(dd->flags & TDES_FLAGS_FAST)) {
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dma_sync_single_for_device(dd->dev, dma_addr_in, length,
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DMA_TO_DEVICE);
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}
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switch (rctx->mode & TDES_FLAGS_OPMODE_MASK) {
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case TDES_FLAGS_CFB8:
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addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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break;
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case TDES_FLAGS_CFB16:
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addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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default:
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addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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}
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dd->dma_lch_in.dma_conf.dst_addr_width = addr_width;
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dd->dma_lch_out.dma_conf.src_addr_width = addr_width;
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dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
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dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf);
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dd->flags |= TDES_FLAGS_DMA;
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sg_init_table(&sg[0], 1);
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sg_dma_address(&sg[0]) = dma_addr_in;
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sg_dma_len(&sg[0]) = length;
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sg_init_table(&sg[1], 1);
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sg_dma_address(&sg[1]) = dma_addr_out;
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sg_dma_len(&sg[1]) = length;
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in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg[0],
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1, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!in_desc)
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return -EINVAL;
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out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg[1],
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1, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!out_desc)
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return -EINVAL;
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out_desc->callback = atmel_tdes_dma_callback;
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out_desc->callback_param = dd;
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dmaengine_submit(out_desc);
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dma_async_issue_pending(dd->dma_lch_out.chan);
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dmaengine_submit(in_desc);
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dma_async_issue_pending(dd->dma_lch_in.chan);
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return 0;
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}
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static int atmel_tdes_crypt_start(struct atmel_tdes_dev *dd)
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{
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int err, fast = 0, in, out;
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size_t count;
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dma_addr_t addr_in, addr_out;
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|
|
if ((!dd->in_offset) && (!dd->out_offset)) {
|
|
/* check for alignment */
|
|
in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32)) &&
|
|
IS_ALIGNED(dd->in_sg->length, dd->ctx->block_size);
|
|
out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32)) &&
|
|
IS_ALIGNED(dd->out_sg->length, dd->ctx->block_size);
|
|
fast = in && out;
|
|
|
|
if (sg_dma_len(dd->in_sg) != sg_dma_len(dd->out_sg))
|
|
fast = 0;
|
|
}
|
|
|
|
|
|
if (fast) {
|
|
count = min_t(size_t, dd->total, sg_dma_len(dd->in_sg));
|
|
count = min_t(size_t, count, sg_dma_len(dd->out_sg));
|
|
|
|
err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
if (!err) {
|
|
dev_dbg(dd->dev, "dma_map_sg() error\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = dma_map_sg(dd->dev, dd->out_sg, 1,
|
|
DMA_FROM_DEVICE);
|
|
if (!err) {
|
|
dev_dbg(dd->dev, "dma_map_sg() error\n");
|
|
dma_unmap_sg(dd->dev, dd->in_sg, 1,
|
|
DMA_TO_DEVICE);
|
|
return -EINVAL;
|
|
}
|
|
|
|
addr_in = sg_dma_address(dd->in_sg);
|
|
addr_out = sg_dma_address(dd->out_sg);
|
|
|
|
dd->flags |= TDES_FLAGS_FAST;
|
|
|
|
} else {
|
|
/* use cache buffers */
|
|
count = atmel_tdes_sg_copy(&dd->in_sg, &dd->in_offset,
|
|
dd->buf_in, dd->buflen, dd->total, 0);
|
|
|
|
addr_in = dd->dma_addr_in;
|
|
addr_out = dd->dma_addr_out;
|
|
|
|
dd->flags &= ~TDES_FLAGS_FAST;
|
|
}
|
|
|
|
dd->total -= count;
|
|
|
|
if (dd->caps.has_dma)
|
|
err = atmel_tdes_crypt_dma(dd, addr_in, addr_out, count);
|
|
else
|
|
err = atmel_tdes_crypt_pdc(dd, addr_in, addr_out, count);
|
|
|
|
if (err && (dd->flags & TDES_FLAGS_FAST)) {
|
|
dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void
|
|
atmel_tdes_set_iv_as_last_ciphertext_block(struct atmel_tdes_dev *dd)
|
|
{
|
|
struct skcipher_request *req = dd->req;
|
|
struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
|
|
struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
|
|
unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
|
|
|
|
if (req->cryptlen < ivsize)
|
|
return;
|
|
|
|
if (rctx->mode & TDES_FLAGS_ENCRYPT) {
|
|
scatterwalk_map_and_copy(req->iv, req->dst,
|
|
req->cryptlen - ivsize, ivsize, 0);
|
|
} else {
|
|
if (req->src == req->dst)
|
|
memcpy(req->iv, rctx->lastc, ivsize);
|
|
else
|
|
scatterwalk_map_and_copy(req->iv, req->src,
|
|
req->cryptlen - ivsize,
|
|
ivsize, 0);
|
|
}
|
|
}
|
|
|
|
static void atmel_tdes_finish_req(struct atmel_tdes_dev *dd, int err)
|
|
{
|
|
struct skcipher_request *req = dd->req;
|
|
struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
|
|
|
|
clk_disable_unprepare(dd->iclk);
|
|
|
|
dd->flags &= ~TDES_FLAGS_BUSY;
|
|
|
|
if (!err && (rctx->mode & TDES_FLAGS_OPMODE_MASK) != TDES_FLAGS_ECB)
|
|
atmel_tdes_set_iv_as_last_ciphertext_block(dd);
|
|
|
|
req->base.complete(&req->base, err);
|
|
}
|
|
|
|
static int atmel_tdes_handle_queue(struct atmel_tdes_dev *dd,
|
|
struct skcipher_request *req)
|
|
{
|
|
struct crypto_async_request *async_req, *backlog;
|
|
struct atmel_tdes_ctx *ctx;
|
|
struct atmel_tdes_reqctx *rctx;
|
|
unsigned long flags;
|
|
int err, ret = 0;
|
|
|
|
spin_lock_irqsave(&dd->lock, flags);
|
|
if (req)
|
|
ret = crypto_enqueue_request(&dd->queue, &req->base);
|
|
if (dd->flags & TDES_FLAGS_BUSY) {
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
return ret;
|
|
}
|
|
backlog = crypto_get_backlog(&dd->queue);
|
|
async_req = crypto_dequeue_request(&dd->queue);
|
|
if (async_req)
|
|
dd->flags |= TDES_FLAGS_BUSY;
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
if (!async_req)
|
|
return ret;
|
|
|
|
if (backlog)
|
|
backlog->complete(backlog, -EINPROGRESS);
|
|
|
|
req = skcipher_request_cast(async_req);
|
|
|
|
/* assign new request to device */
|
|
dd->req = req;
|
|
dd->total = req->cryptlen;
|
|
dd->in_offset = 0;
|
|
dd->in_sg = req->src;
|
|
dd->out_offset = 0;
|
|
dd->out_sg = req->dst;
|
|
|
|
rctx = skcipher_request_ctx(req);
|
|
ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
|
|
rctx->mode &= TDES_FLAGS_MODE_MASK;
|
|
dd->flags = (dd->flags & ~TDES_FLAGS_MODE_MASK) | rctx->mode;
|
|
dd->ctx = ctx;
|
|
|
|
err = atmel_tdes_write_ctrl(dd);
|
|
if (!err)
|
|
err = atmel_tdes_crypt_start(dd);
|
|
if (err) {
|
|
/* des_task will not finish it, so do it here */
|
|
atmel_tdes_finish_req(dd, err);
|
|
tasklet_schedule(&dd->queue_task);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int atmel_tdes_crypt_dma_stop(struct atmel_tdes_dev *dd)
|
|
{
|
|
int err = -EINVAL;
|
|
size_t count;
|
|
|
|
if (dd->flags & TDES_FLAGS_DMA) {
|
|
err = 0;
|
|
if (dd->flags & TDES_FLAGS_FAST) {
|
|
dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
|
|
dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
|
|
} else {
|
|
dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
|
|
dd->dma_size, DMA_FROM_DEVICE);
|
|
|
|
/* copy data */
|
|
count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
|
|
dd->buf_out, dd->buflen, dd->dma_size, 1);
|
|
if (count != dd->dma_size) {
|
|
err = -EINVAL;
|
|
dev_dbg(dd->dev, "not all data converted: %zu\n", count);
|
|
}
|
|
}
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static int atmel_tdes_crypt(struct skcipher_request *req, unsigned long mode)
|
|
{
|
|
struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
|
|
struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(skcipher);
|
|
struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
|
|
struct device *dev = ctx->dd->dev;
|
|
|
|
if (!req->cryptlen)
|
|
return 0;
|
|
|
|
switch (mode & TDES_FLAGS_OPMODE_MASK) {
|
|
case TDES_FLAGS_CFB8:
|
|
if (!IS_ALIGNED(req->cryptlen, CFB8_BLOCK_SIZE)) {
|
|
dev_dbg(dev, "request size is not exact amount of CFB8 blocks\n");
|
|
return -EINVAL;
|
|
}
|
|
ctx->block_size = CFB8_BLOCK_SIZE;
|
|
break;
|
|
|
|
case TDES_FLAGS_CFB16:
|
|
if (!IS_ALIGNED(req->cryptlen, CFB16_BLOCK_SIZE)) {
|
|
dev_dbg(dev, "request size is not exact amount of CFB16 blocks\n");
|
|
return -EINVAL;
|
|
}
|
|
ctx->block_size = CFB16_BLOCK_SIZE;
|
|
break;
|
|
|
|
case TDES_FLAGS_CFB32:
|
|
if (!IS_ALIGNED(req->cryptlen, CFB32_BLOCK_SIZE)) {
|
|
dev_dbg(dev, "request size is not exact amount of CFB32 blocks\n");
|
|
return -EINVAL;
|
|
}
|
|
ctx->block_size = CFB32_BLOCK_SIZE;
|
|
break;
|
|
|
|
default:
|
|
if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE)) {
|
|
dev_dbg(dev, "request size is not exact amount of DES blocks\n");
|
|
return -EINVAL;
|
|
}
|
|
ctx->block_size = DES_BLOCK_SIZE;
|
|
break;
|
|
}
|
|
|
|
rctx->mode = mode;
|
|
|
|
if ((mode & TDES_FLAGS_OPMODE_MASK) != TDES_FLAGS_ECB &&
|
|
!(mode & TDES_FLAGS_ENCRYPT) && req->src == req->dst) {
|
|
unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
|
|
|
|
if (req->cryptlen >= ivsize)
|
|
scatterwalk_map_and_copy(rctx->lastc, req->src,
|
|
req->cryptlen - ivsize,
|
|
ivsize, 0);
|
|
}
|
|
|
|
return atmel_tdes_handle_queue(ctx->dd, req);
|
|
}
|
|
|
|
static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
|
|
{
|
|
int ret;
|
|
|
|
/* Try to grab 2 DMA channels */
|
|
dd->dma_lch_in.chan = dma_request_chan(dd->dev, "tx");
|
|
if (IS_ERR(dd->dma_lch_in.chan)) {
|
|
ret = PTR_ERR(dd->dma_lch_in.chan);
|
|
goto err_dma_in;
|
|
}
|
|
|
|
dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
|
|
TDES_IDATA1R;
|
|
dd->dma_lch_in.dma_conf.src_maxburst = 1;
|
|
dd->dma_lch_in.dma_conf.src_addr_width =
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
dd->dma_lch_in.dma_conf.dst_maxburst = 1;
|
|
dd->dma_lch_in.dma_conf.dst_addr_width =
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
dd->dma_lch_in.dma_conf.device_fc = false;
|
|
|
|
dd->dma_lch_out.chan = dma_request_chan(dd->dev, "rx");
|
|
if (IS_ERR(dd->dma_lch_out.chan)) {
|
|
ret = PTR_ERR(dd->dma_lch_out.chan);
|
|
goto err_dma_out;
|
|
}
|
|
|
|
dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
|
|
TDES_ODATA1R;
|
|
dd->dma_lch_out.dma_conf.src_maxburst = 1;
|
|
dd->dma_lch_out.dma_conf.src_addr_width =
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
dd->dma_lch_out.dma_conf.dst_maxburst = 1;
|
|
dd->dma_lch_out.dma_conf.dst_addr_width =
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
dd->dma_lch_out.dma_conf.device_fc = false;
|
|
|
|
return 0;
|
|
|
|
err_dma_out:
|
|
dma_release_channel(dd->dma_lch_in.chan);
|
|
err_dma_in:
|
|
dev_err(dd->dev, "no DMA channel available\n");
|
|
return ret;
|
|
}
|
|
|
|
static void atmel_tdes_dma_cleanup(struct atmel_tdes_dev *dd)
|
|
{
|
|
dma_release_channel(dd->dma_lch_in.chan);
|
|
dma_release_channel(dd->dma_lch_out.chan);
|
|
}
|
|
|
|
static int atmel_des_setkey(struct crypto_skcipher *tfm, const u8 *key,
|
|
unsigned int keylen)
|
|
{
|
|
struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
|
|
int err;
|
|
|
|
err = verify_skcipher_des_key(tfm, key);
|
|
if (err)
|
|
return err;
|
|
|
|
memcpy(ctx->key, key, keylen);
|
|
ctx->keylen = keylen;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_tdes_setkey(struct crypto_skcipher *tfm, const u8 *key,
|
|
unsigned int keylen)
|
|
{
|
|
struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
|
|
int err;
|
|
|
|
err = verify_skcipher_des3_key(tfm, key);
|
|
if (err)
|
|
return err;
|
|
|
|
memcpy(ctx->key, key, keylen);
|
|
ctx->keylen = keylen;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_tdes_ecb_encrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_ECB | TDES_FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int atmel_tdes_ecb_decrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_ECB);
|
|
}
|
|
|
|
static int atmel_tdes_cbc_encrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CBC | TDES_FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int atmel_tdes_cbc_decrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CBC);
|
|
}
|
|
static int atmel_tdes_cfb_encrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB64 | TDES_FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int atmel_tdes_cfb_decrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB64);
|
|
}
|
|
|
|
static int atmel_tdes_cfb8_encrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB8 | TDES_FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int atmel_tdes_cfb8_decrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB8);
|
|
}
|
|
|
|
static int atmel_tdes_cfb16_encrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB16 | TDES_FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int atmel_tdes_cfb16_decrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB16);
|
|
}
|
|
|
|
static int atmel_tdes_cfb32_encrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB32 | TDES_FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int atmel_tdes_cfb32_decrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_CFB32);
|
|
}
|
|
|
|
static int atmel_tdes_ofb_encrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_OFB | TDES_FLAGS_ENCRYPT);
|
|
}
|
|
|
|
static int atmel_tdes_ofb_decrypt(struct skcipher_request *req)
|
|
{
|
|
return atmel_tdes_crypt(req, TDES_FLAGS_OFB);
|
|
}
|
|
|
|
static int atmel_tdes_init_tfm(struct crypto_skcipher *tfm)
|
|
{
|
|
struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
|
|
|
|
ctx->dd = atmel_tdes_dev_alloc();
|
|
if (!ctx->dd)
|
|
return -ENODEV;
|
|
|
|
crypto_skcipher_set_reqsize(tfm, sizeof(struct atmel_tdes_reqctx));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_tdes_skcipher_alg_init(struct skcipher_alg *alg)
|
|
{
|
|
alg->base.cra_priority = ATMEL_TDES_PRIORITY;
|
|
alg->base.cra_flags = CRYPTO_ALG_ASYNC;
|
|
alg->base.cra_ctxsize = sizeof(struct atmel_tdes_ctx);
|
|
alg->base.cra_module = THIS_MODULE;
|
|
|
|
alg->init = atmel_tdes_init_tfm;
|
|
}
|
|
|
|
static struct skcipher_alg tdes_algs[] = {
|
|
{
|
|
.base.cra_name = "ecb(des)",
|
|
.base.cra_driver_name = "atmel-ecb-des",
|
|
.base.cra_blocksize = DES_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x7,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.setkey = atmel_des_setkey,
|
|
.encrypt = atmel_tdes_ecb_encrypt,
|
|
.decrypt = atmel_tdes_ecb_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "cbc(des)",
|
|
.base.cra_driver_name = "atmel-cbc-des",
|
|
.base.cra_blocksize = DES_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x7,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.setkey = atmel_des_setkey,
|
|
.encrypt = atmel_tdes_cbc_encrypt,
|
|
.decrypt = atmel_tdes_cbc_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "cfb(des)",
|
|
.base.cra_driver_name = "atmel-cfb-des",
|
|
.base.cra_blocksize = DES_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x7,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.setkey = atmel_des_setkey,
|
|
.encrypt = atmel_tdes_cfb_encrypt,
|
|
.decrypt = atmel_tdes_cfb_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "cfb8(des)",
|
|
.base.cra_driver_name = "atmel-cfb8-des",
|
|
.base.cra_blocksize = CFB8_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.setkey = atmel_des_setkey,
|
|
.encrypt = atmel_tdes_cfb8_encrypt,
|
|
.decrypt = atmel_tdes_cfb8_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "cfb16(des)",
|
|
.base.cra_driver_name = "atmel-cfb16-des",
|
|
.base.cra_blocksize = CFB16_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x1,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.setkey = atmel_des_setkey,
|
|
.encrypt = atmel_tdes_cfb16_encrypt,
|
|
.decrypt = atmel_tdes_cfb16_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "cfb32(des)",
|
|
.base.cra_driver_name = "atmel-cfb32-des",
|
|
.base.cra_blocksize = CFB32_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x3,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.setkey = atmel_des_setkey,
|
|
.encrypt = atmel_tdes_cfb32_encrypt,
|
|
.decrypt = atmel_tdes_cfb32_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "ofb(des)",
|
|
.base.cra_driver_name = "atmel-ofb-des",
|
|
.base.cra_blocksize = 1,
|
|
.base.cra_alignmask = 0x7,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
.max_keysize = DES_KEY_SIZE,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
.setkey = atmel_des_setkey,
|
|
.encrypt = atmel_tdes_ofb_encrypt,
|
|
.decrypt = atmel_tdes_ofb_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "ecb(des3_ede)",
|
|
.base.cra_driver_name = "atmel-ecb-tdes",
|
|
.base.cra_blocksize = DES_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x7,
|
|
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
.setkey = atmel_tdes_setkey,
|
|
.encrypt = atmel_tdes_ecb_encrypt,
|
|
.decrypt = atmel_tdes_ecb_decrypt,
|
|
},
|
|
{
|
|
.base.cra_name = "cbc(des3_ede)",
|
|
.base.cra_driver_name = "atmel-cbc-tdes",
|
|
.base.cra_blocksize = DES_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x7,
|
|
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
.setkey = atmel_tdes_setkey,
|
|
.encrypt = atmel_tdes_cbc_encrypt,
|
|
.decrypt = atmel_tdes_cbc_decrypt,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
},
|
|
{
|
|
.base.cra_name = "ofb(des3_ede)",
|
|
.base.cra_driver_name = "atmel-ofb-tdes",
|
|
.base.cra_blocksize = DES_BLOCK_SIZE,
|
|
.base.cra_alignmask = 0x7,
|
|
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
.setkey = atmel_tdes_setkey,
|
|
.encrypt = atmel_tdes_ofb_encrypt,
|
|
.decrypt = atmel_tdes_ofb_decrypt,
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
},
|
|
};
|
|
|
|
static void atmel_tdes_queue_task(unsigned long data)
|
|
{
|
|
struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *)data;
|
|
|
|
atmel_tdes_handle_queue(dd, NULL);
|
|
}
|
|
|
|
static void atmel_tdes_done_task(unsigned long data)
|
|
{
|
|
struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *) data;
|
|
int err;
|
|
|
|
if (!(dd->flags & TDES_FLAGS_DMA))
|
|
err = atmel_tdes_crypt_pdc_stop(dd);
|
|
else
|
|
err = atmel_tdes_crypt_dma_stop(dd);
|
|
|
|
if (dd->total && !err) {
|
|
if (dd->flags & TDES_FLAGS_FAST) {
|
|
dd->in_sg = sg_next(dd->in_sg);
|
|
dd->out_sg = sg_next(dd->out_sg);
|
|
if (!dd->in_sg || !dd->out_sg)
|
|
err = -EINVAL;
|
|
}
|
|
if (!err)
|
|
err = atmel_tdes_crypt_start(dd);
|
|
if (!err)
|
|
return; /* DMA started. Not fininishing. */
|
|
}
|
|
|
|
atmel_tdes_finish_req(dd, err);
|
|
atmel_tdes_handle_queue(dd, NULL);
|
|
}
|
|
|
|
static irqreturn_t atmel_tdes_irq(int irq, void *dev_id)
|
|
{
|
|
struct atmel_tdes_dev *tdes_dd = dev_id;
|
|
u32 reg;
|
|
|
|
reg = atmel_tdes_read(tdes_dd, TDES_ISR);
|
|
if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) {
|
|
atmel_tdes_write(tdes_dd, TDES_IDR, reg);
|
|
if (TDES_FLAGS_BUSY & tdes_dd->flags)
|
|
tasklet_schedule(&tdes_dd->done_task);
|
|
else
|
|
dev_warn(tdes_dd->dev, "TDES interrupt when no active requests.\n");
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
static void atmel_tdes_unregister_algs(struct atmel_tdes_dev *dd)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(tdes_algs); i++)
|
|
crypto_unregister_skcipher(&tdes_algs[i]);
|
|
}
|
|
|
|
static int atmel_tdes_register_algs(struct atmel_tdes_dev *dd)
|
|
{
|
|
int err, i, j;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) {
|
|
atmel_tdes_skcipher_alg_init(&tdes_algs[i]);
|
|
|
|
err = crypto_register_skcipher(&tdes_algs[i]);
|
|
if (err)
|
|
goto err_tdes_algs;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_tdes_algs:
|
|
for (j = 0; j < i; j++)
|
|
crypto_unregister_skcipher(&tdes_algs[j]);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd)
|
|
{
|
|
|
|
dd->caps.has_dma = 0;
|
|
dd->caps.has_cfb_3keys = 0;
|
|
|
|
/* keep only major version number */
|
|
switch (dd->hw_version & 0xf00) {
|
|
case 0x700:
|
|
dd->caps.has_dma = 1;
|
|
dd->caps.has_cfb_3keys = 1;
|
|
break;
|
|
case 0x600:
|
|
break;
|
|
default:
|
|
dev_warn(dd->dev,
|
|
"Unmanaged tdes version, set minimum capabilities\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_OF)
|
|
static const struct of_device_id atmel_tdes_dt_ids[] = {
|
|
{ .compatible = "atmel,at91sam9g46-tdes" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, atmel_tdes_dt_ids);
|
|
#endif
|
|
|
|
static int atmel_tdes_probe(struct platform_device *pdev)
|
|
{
|
|
struct atmel_tdes_dev *tdes_dd;
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *tdes_res;
|
|
int err;
|
|
|
|
tdes_dd = devm_kmalloc(&pdev->dev, sizeof(*tdes_dd), GFP_KERNEL);
|
|
if (!tdes_dd)
|
|
return -ENOMEM;
|
|
|
|
tdes_dd->dev = dev;
|
|
|
|
platform_set_drvdata(pdev, tdes_dd);
|
|
|
|
INIT_LIST_HEAD(&tdes_dd->list);
|
|
spin_lock_init(&tdes_dd->lock);
|
|
|
|
tasklet_init(&tdes_dd->done_task, atmel_tdes_done_task,
|
|
(unsigned long)tdes_dd);
|
|
tasklet_init(&tdes_dd->queue_task, atmel_tdes_queue_task,
|
|
(unsigned long)tdes_dd);
|
|
|
|
crypto_init_queue(&tdes_dd->queue, ATMEL_TDES_QUEUE_LENGTH);
|
|
|
|
/* Get the base address */
|
|
tdes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!tdes_res) {
|
|
dev_err(dev, "no MEM resource info\n");
|
|
err = -ENODEV;
|
|
goto err_tasklet_kill;
|
|
}
|
|
tdes_dd->phys_base = tdes_res->start;
|
|
|
|
/* Get the IRQ */
|
|
tdes_dd->irq = platform_get_irq(pdev, 0);
|
|
if (tdes_dd->irq < 0) {
|
|
err = tdes_dd->irq;
|
|
goto err_tasklet_kill;
|
|
}
|
|
|
|
err = devm_request_irq(&pdev->dev, tdes_dd->irq, atmel_tdes_irq,
|
|
IRQF_SHARED, "atmel-tdes", tdes_dd);
|
|
if (err) {
|
|
dev_err(dev, "unable to request tdes irq.\n");
|
|
goto err_tasklet_kill;
|
|
}
|
|
|
|
/* Initializing the clock */
|
|
tdes_dd->iclk = devm_clk_get(&pdev->dev, "tdes_clk");
|
|
if (IS_ERR(tdes_dd->iclk)) {
|
|
dev_err(dev, "clock initialization failed.\n");
|
|
err = PTR_ERR(tdes_dd->iclk);
|
|
goto err_tasklet_kill;
|
|
}
|
|
|
|
tdes_dd->io_base = devm_ioremap_resource(&pdev->dev, tdes_res);
|
|
if (IS_ERR(tdes_dd->io_base)) {
|
|
err = PTR_ERR(tdes_dd->io_base);
|
|
goto err_tasklet_kill;
|
|
}
|
|
|
|
err = atmel_tdes_hw_version_init(tdes_dd);
|
|
if (err)
|
|
goto err_tasklet_kill;
|
|
|
|
atmel_tdes_get_cap(tdes_dd);
|
|
|
|
err = atmel_tdes_buff_init(tdes_dd);
|
|
if (err)
|
|
goto err_tasklet_kill;
|
|
|
|
if (tdes_dd->caps.has_dma) {
|
|
err = atmel_tdes_dma_init(tdes_dd);
|
|
if (err)
|
|
goto err_buff_cleanup;
|
|
|
|
dev_info(dev, "using %s, %s for DMA transfers\n",
|
|
dma_chan_name(tdes_dd->dma_lch_in.chan),
|
|
dma_chan_name(tdes_dd->dma_lch_out.chan));
|
|
}
|
|
|
|
spin_lock(&atmel_tdes.lock);
|
|
list_add_tail(&tdes_dd->list, &atmel_tdes.dev_list);
|
|
spin_unlock(&atmel_tdes.lock);
|
|
|
|
err = atmel_tdes_register_algs(tdes_dd);
|
|
if (err)
|
|
goto err_algs;
|
|
|
|
dev_info(dev, "Atmel DES/TDES\n");
|
|
|
|
return 0;
|
|
|
|
err_algs:
|
|
spin_lock(&atmel_tdes.lock);
|
|
list_del(&tdes_dd->list);
|
|
spin_unlock(&atmel_tdes.lock);
|
|
if (tdes_dd->caps.has_dma)
|
|
atmel_tdes_dma_cleanup(tdes_dd);
|
|
err_buff_cleanup:
|
|
atmel_tdes_buff_cleanup(tdes_dd);
|
|
err_tasklet_kill:
|
|
tasklet_kill(&tdes_dd->done_task);
|
|
tasklet_kill(&tdes_dd->queue_task);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int atmel_tdes_remove(struct platform_device *pdev)
|
|
{
|
|
struct atmel_tdes_dev *tdes_dd;
|
|
|
|
tdes_dd = platform_get_drvdata(pdev);
|
|
if (!tdes_dd)
|
|
return -ENODEV;
|
|
spin_lock(&atmel_tdes.lock);
|
|
list_del(&tdes_dd->list);
|
|
spin_unlock(&atmel_tdes.lock);
|
|
|
|
atmel_tdes_unregister_algs(tdes_dd);
|
|
|
|
tasklet_kill(&tdes_dd->done_task);
|
|
tasklet_kill(&tdes_dd->queue_task);
|
|
|
|
if (tdes_dd->caps.has_dma)
|
|
atmel_tdes_dma_cleanup(tdes_dd);
|
|
|
|
atmel_tdes_buff_cleanup(tdes_dd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver atmel_tdes_driver = {
|
|
.probe = atmel_tdes_probe,
|
|
.remove = atmel_tdes_remove,
|
|
.driver = {
|
|
.name = "atmel_tdes",
|
|
.of_match_table = of_match_ptr(atmel_tdes_dt_ids),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(atmel_tdes_driver);
|
|
|
|
MODULE_DESCRIPTION("Atmel DES/TDES hw acceleration support.");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
|